LT1074CK datasheet(12/16 Pages) LINER

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LT1074/LT1076

Figure 10. Error Amplifier

DESCRIPTIO S

at mid frequencies

R at high frequencies

••

=•

Phase shift from the FB pin to the VC pin is 90° at mid

frequencies where the external CC is controlling gain, then

drops back to 0

° (actually 180° since FB is an inverting

input) when the reactance of CC is small compared to RC.

The low frequency “pole” where the reactance of CC is

equal to the output impedance of Q4 and Q6 (rO), is:

POLE

••

≈Ω

400

Although fPOLE varies as much as 3:1 due to rO variations,

mid-frequency gain is dependent only on Gm, which is

specified much tighter on the data sheet. The higher

frequency “zero” is determined solely by RC and CC.

ZERO

••

The error amplifier has asymmetrical peak output current.

Q3 and Q4 current mirrors are unity-gain, but the Q6

mirror has a gain of 1.8 at output null and a gain of 8 when

the FB pin is high (Q1 current = 0). This results in a

maximum positive output current of 140

µA and a maxi-

mum negative (sink) output current of

≅1.1mA.Theasym-

metry is deliberate—it results in much less regulator

output overshoot during rapid start-up or following the

release of an output overload. Amplifier offset is kept low

by area scaling Q1 and Q2 at 1.8:1.

Amplifier swing is limited by the internal 5.8V supply for

positive outputs and by D1 and D2 when the output goes

low. Low clamp voltage is approximately one diode drop

(

≈0.7V – 2mV/°C).

Note that both the FB pin and the VC pin have other internal

connections. Refer to the frequency shifting and synchro-

nizing discussions.

140 A

LT1074 • PD11

50 A

90 A

300

5.8V

50 A

2.21V

EXTERNAL

FREQUENCY

COMPENSATION

90 A

Ω

X1.8

ALL CURRENTS SHOWN ARE AT NULL CONDITION

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