LT1786FCS datasheet(8/20 Pages) LINER

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LT1786F

PIN FUNCTIONS

AGND (Pin 5): This is the low current analog ground. It is

the negative sense terminal for the internal 1.24V refer-

ence and the ICCFL summing voltage in the LT1786F.

Connect low current signal paths that terminate to ground

and frequency compensation components that terminate

to ground directly to this pin for best regulation and

performance.

SHDN (Pin 6): Pulling this pin low causes regulator

shutdown with quiescent current typically reduced to

150

µA. In this condition, the DAC circuitry remains alive

and the DAC IOUT level is maintained. If this pin is not used,

use a pull-up resistor to force a logic high level (maximum

of 6V). The pin can be floated and an internal current

source will pull the pin to a logic high level. However, poor

PCB layout techniques can permit switching noise to inject

into this pin and cause erratic operation. LTC recommends

the use of a pull-up resistor. If the SMBSUS pin is pulled

low or Bit 7 = 1 in the Command Byte, complete IC

shutdown is enabled. An internal open drain N-channel

device turns on and pulls the SHDN pin low. The N-channel

can sink up to 1.6mA.

SMBSUS (Pin 7): Pulling this pin low causes complete

shutdown for the IC with quiescent current typically

reduced to 40

µA. In this SMBus suspend condition, the

DAC retains its last output current setting and returns to

this level when the logic low signal at this pin is removed.

If this pin is not used, use a pull-up resistor to force a

logic high level or tie it directly to VCC. Poor PCB layout

techniques can permit switching noise to inject into this

pin and cause erratic operation. A small value capacitor

may be required to filter out this noise. Setting Bit 7 = 1

in the Command Byte also enables an SMBus suspend

condition. Enabling an SMBus suspend condition turns

on an internal open drain N-channel device which pulls

the SHDN pin low. The N-channel device sinks up to

1.6mA at the SHDN pin.

ADR (Pin 8): This is the SMBus address select pin. Tie this

pin to either VCC or GND to select one of two SMBus

addresses to which the LT1786F will respond. If the ADR

pin is tied to GND, the SMBus address is set to 58 (HEX)

and the DAC IOUT powers up to zero scale. If the ADR pin

is tied to VCC, the SMBus address is set to 5A (HEX) and

the DAC IOUT powers up to half scale. If a different value is

required for the DAC IOUT on power-up, use the SHDN pin

to keep the CCFL regulator off until the required value has

been programmed for the DAC via the SMBus.

SDA (Pin 9): This is the SMBus bidirectional data input and

digital output pin. Data is shifted into the SDA pin and

acknowledged by the SDA pin. SDA is a high impedance

pin while data is shifted into the pin and an open-drain

N-channel output during acknowledges. SDA requires a

pull-up resistor or current source to VCC.

SCL (Pin 10): This is the SMBus clock input pin. Data is

shifted into the SDA pin at the rising edges of the SCL clock

during data transfer. SCL is a high impedance pin. SCL

requires a pull-up resistor or current source to VCC.

IOUT (Pin 11): This pin is the current output for the DAC and

provides a full-scale output current of 100

µA ±4µA over

temperature. Initial accuracy is 100

µA ±2µA.The pin can

be biased from – 10V to (VCC – 1.3V). This pin is typically

tied directly to the ICCFL pin and provides the programming

current which sets the operating lamp current. The IOUT

pin has very little bias voltage change when tied to the ICCFL

pin as ICCFL is regulated. The programming current is

sourced from the IOUT pin and sunk by the ICCFL pin.

VCC (Pin 12): This is the supply pin for the LT1786F. The

IC accepts an input voltage range of 3V minimum to 6.5V

maximum with little change in quiescent current (zero

switch current). An internal, low-dropout regulator pro-

vides a 2.4V supply for most of the internal circuitry.

Supply current increases as switch current increases at a

rate approximately 1/50 of switch current. This corre-

sponds to a forced Beta of 50 for the power switch. The IC

incorporates undervoltage lockout by sensing regulator

dropout and locking out switching for input voltages

below 2.5V. Hysteresis is not used to maximize the range

of input voltage. The typical input voltage is a 3.3V or 5V

logic supply.

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