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932SQL450 Datasheet(PDF) 11 Page - Integrated Device Technology

Part # 932SQL450
Description  Integrated 85 ohm differential terminations
PDF  23 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

932SQL450 Datasheet(HTML) 11 Page - Integrated Device Technology

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REVISION B 03/06/15
11
LOW-POWER CK420BQ DERIVATIVE FOR PCIE COMMON CLOCK ARCHITECTURES
932SQL450 DATASHEET
NOTE: Pin numbers refer to TSSOP
SMBus Table: Output Enable Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
DOT96 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 6
NS_SAS1 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 5
NS_SAS0 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 4
NS_SRC1 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 3
NS_SRC0 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 2
SRC2 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 1
SRC1 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 0
SRC0 Enable
Output Enable
RW
Disable-Low/Low
Enable
1
SMBus Table: Output Enable Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
REF14_3x Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 6
0
Bit 5
0
Bit 4
CPU3
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 3
CPU2
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 2
CPU1
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 1
CPU0
Output Enable
RW
Disable-Low/Low
Enable
1
Bit 0
Spread Spectrum Enable
Spread Off/On
RW
Spread Off
Spread On
0
SMBus Table: Output Enable Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
PCI4 Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 4
PCI3 Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 3
PCI2 Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 2
PCI1 Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 1
PCI0 Enable
Output Enable
RW
Disable-Low
Enable
1
Bit 0
48MHz Enable
Output Enable
RW
Disable-Low
Enable
1
SMBus Table: Differential Amplitude Control
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
CPU AMPLITUDE 1
RW
00 = 700mV
01 = 800mV
0
Bit 6
CPU AMPLITUDE 0
RW
10 = 900mV
11 = 1000mV
1
Bit 5
SRC AMPLITUDE 1
RW
00 = 700mV
01 = 800mV
0
Bit 4
SRC AMPLITUDE 0
RW
10 = 900mV
11 = 1000mV
1
Bit 3
DOT96 AMPLITUDE 1
RW
00 = 700mV
01 = 800mV
0
Bit 2
DOT96 AMPLITUDE 0
RW
10 = 900mV
11 = 1000mV
1
Bit 1
NS-SAS/SRC AMPLITUDE 1
RW
00 = 700mV
01 = 800mV
0
Bit 0
NS-SAS/SRC AMPLITUDE 0
RW
10 = 900mV
11 = 1000mV
1
SMBus Table: Spread Amount Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
SS AMOUNT[1]
RW
00= -0.2%
10= -0.4%
1
Bit 0
SS AMOUNT[0]
RW
01= -0.3%
11= -0.5%
1
RESERVED
RESERVED
30/31
Byte 1
62/61
14
RESERVED
RESERVED
RESERVED
16
54/53
Byte 2
Byte 3
Byte 4
17
21
Byte 0
24/25
48/47
44/43
50/49
60/59
15
36/35
34/33
5
13
CPU/SRC/
PCI
56/55
42/41
RESERVED
RESERVED
CPU Vhigh
SRC Vhigh
DOT96 Vhigh
NS-SAS/SRC Vhigh
RESERVED
RESERVED
Spread Amount (note
B1b0 must be set to '1')
RESERVED



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