PIC16LC62B datasheet(59/120 Pages) MICROCHIP

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PIC16C62B/72A

Preliminary

DS35008B-page 59

10.4

Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will elimi-

nate external RC components usually needed to create

a Power-on Reset. A maximum rise time for VDD is

specified (SVDD, parameter D004). For a slow rise

time, see Figure 10-6.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature,...) must be met to ensure oper-

ation. If these conditions are not met, the device must

be held in reset until the operating conditions are met.

Brown-out Reset may be used to meet the start-up con-

ditions.

FIGURE 10-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

10.5

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(TPWRT, parameter #33) from the POR. The Power-up

Timer operates on an internal RC oscillator. The chip is

kept in reset as long as the PWRT is active. The

PWRT’s time delay allows VDD to rise to an acceptable

level. A configuration bit is provided to enable/disable

the PWRT.

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See DC

parameters for details.

10.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a delay of

1024 oscillator cycles (from OSC1 input) after the

PWRT delay is over (TOST, parameter #32). This

ensures that the crystal oscillator or resonator has

started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

10.7

Brown-Out Reset (BOR)

The configuration bit, BODEN, can enable or disable

the Brown-Out Reset circuit. If VPP falls below Vbor

(parameter #35, about 100

µS), the brown-out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a reset may not occur.

Once the brown-out occurs, the device will remain in

brown-out reset until VDD rises above VBOR. The

power-up timer then keeps the device in reset for

TPWRT (parameter #33, about 72mS). If VDD should fall

below VBOR during TPWRT, the brown-out reset pro-

cess will restart when VDD rises above VBOR with the

power-up timer reset. The power-up timer is always

enabled when the brown-out reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

Note 1: External Power-on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k

Ω is recommended to make sure

that voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100

Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC16CXX

Note:

The OST delay may not occur when the

device wakes from SLEEP.

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