PIC17C42A datasheet(2/16 Pages) MICROCHIP

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PIC17CXX

DS30139I-page 2

The actual programming must be done with VDD in the

VDDP range (4.75 - 5.25V).

VDDP=VDD range required during programming.

VDD min.=minimum operating VDD spec for the part.

VDD max.=maximum operating VCC spec for the part.

Programmers must verify the PIC17CXX at its speci-

ﬁed VDDmax and VDDmin levels. Since Microchip may

introduce future versions of the PIC17CXX with a

broader VDD range, it is best that these levels are user

selectable (defaults are ok).

2.0

PROGRAM MODE ENTRY

To execute the programming routine, the user must

hold TEST pin high, RA2, RA3 must be low and RA4

must be high (after power-up) while keeping MCLR low

and then raise MCLR pin from VIL to VDD or VPP. This

will force FFE0h in the program counter and execution

will begin at that location (the beginning of the boot

code) following reset. Execution is forced to Internal

mode by overriding the fuse conﬁguration. The code

protect bit is not overwritten. The program immediately

polls PORT RB<7:0> to determine a branch address.

Presenting E1h on PORT RB will cause the program to

jump to and execute the “program/verify” routine.

Note:

Any

programmer

not

meeting

these

requirements may only be classiﬁed as

"prototype" or "development" programmer

but not a "production" quality programmer.

All unused pins during programming are in high imped-

ance state.

PORTB (RB) has internal weak pull-ups which are

active during the programming mode. When TEST pin

is high, Power-up timer (PWRT) and Oscillator Start-up

Timers (OST) are disabled.

2.1

Program/Verify Mode

The program/verify mode is intended for full-feature

programmers. This mode offers the following capabili-

ties:

Load any arbitrary 16-bit address to start pro-

gram and/or verify at that location.

Increment address to program/verify the next

location.

Allows arbitrary length programming pulse width.

Following a “verify” allows option to program the

same location or increment and verify the next

location.

Following a “program” allows options to program

the same location again, verify the same loca-

tion or to increment and verify the next location.

Note:

The OSC must not have 72 osc clocks

while the device MCLR is between VIL and

VIHH.

FIGURE 2-1:

PROGRAMMING/VERIFY STATE DIAGRAM

Increment

Address

Program

Verify

Pulse RA1

(Raise RA1

after RA0

↓)

Pulse RA0

(RA0 pulse

width is

programming time)

Pulse

RA1

Pulse

RA1

RA0

↑

Raise RA1

before RA0

↓

Load

Address

Jump to

Program

Routine

Reset

Pulse

RA1

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