PIC17C44-08SLASHP datasheet(26/240 Pages) MICROCHIP

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PIC17C4X

DS30412C-page 26

5.5

RA0/INT Interrupt

The external interrupt on the RA0/INT pin is edge trig-

gered.

Either

the

rising

edge,

INTEDG

bit

(T0STA<7>) is set, or the falling edge, if INTEDG bit is

clear. When a valid edge appears on the RA0/INT pin,

the INTF bit (INTSTA<4>) is set. This interrupt can be

disabled by clearing the INTE control bit (INTSTA<0>).

The INT interrupt can wake the processor from SLEEP.

See Section 14.4 for details on SLEEP operation.

5.6

TMR0 Interrupt

An overﬂow (FFFFh

→ 0000h) in TMR0 will set the

T0IF (INTSTA<5>) bit. The interrupt can be enabled/

disabled by setting/clearing the T0IE control bit

(INTSTA<1>). For operation of the Timer0 module, see

Section 11.0.

5.7

T0CKI Interrupt

The external interrupt on the RA1/T0CKI pin is edge

triggered. Either the rising edge, if the T0SE bit

(T0STA<6>) is set, or the falling edge, if the T0SE bit is

clear. When a valid edge appears on the RA1/T0CKI

pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt

can be disabled by clearing the T0CKIE control bit

(INTSTA<2>). The T0CKI interrupt can wake up the

processor from SLEEP. See Section 14.4 for details on

SLEEP operation.

5.8

Peripheral Interrupt

The peripheral interrupt ﬂag indicates that at least one

of the peripheral interrupts occurred (PEIF is set). The

PEIF bit is a read only bit, and is a bit wise OR of all the

ﬂag bits in the PIR register AND’ed with the corre-

sponding enable bits in the PIE register. Some of the

peripheral interrupts can wake the processor from

SLEEP. See Section 14.4 for details on SLEEP opera-

tion.

FIGURE 5-5:

INT PIN / T0CKI PIN INTERRUPT TIMING

Q3 Q4

OSC1

OSC2

RA0/INT or

RA1/T0CKI

INTF or

T0CKIF

GLINTD

Instruction

executed

System Bus

Instruction

Fetched

PC + 1

Addr (Vector)

Inst (PC)

Inst (PC+1)

Inst (PC)

Dummy

YY + 1

RETFIE

Inst (PC+1)

Inst (Vector)

Addr

Inst (YY + 1)

Dummy

PC + 1

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