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ML4833CS Datasheet(PDF) 6 Page - Micro Linear Corporation |
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ML4833CS Datasheet(HTML) 6 Page - Micro Linear Corporation |
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6 / 13 page ![]() ML4833 6 FUNCTIONAL DESCRIPTION OVERVIEW The ML4833 consists of peak current controlled continuous boost power factor front end section with a flexible ballast control section. Start-up and lamp-out retry timing are controlled by the selection of external timing components, allowing for control of a wide variety of different lamp types. The ballast section controls the lamp power using frequency modulation (FM) with additional programmability provided to adjust the VCO frequency range. This allows for the IC to be used with a variety of different output networks. Figure 1 depicts a detailed block diagram of ML4833. POWER FACTOR SECTION The ML4833 power factor section is a peak current sensing boost mode PFC control circuit in which only voltage loop compensation is needed. It is simpler than a conventional average current control method. It consists of a voltage error amplifier, a current sense amplifier (no compensation is needed), an integrator, a comparator, and a logic control block. In the boost topology, power factor correction is achieved by sensing the output voltage and the current flowing through the current sense resistor. Duty cycle control is achieved by comparing the integrated voltage signal of the error amplifier and the voltage across RSENSE. The duty cycle control timing is shown in Figure 2. Setting minimum input voltage for output regulation can be achieved by selecting CRAMP according to equation 1. C PEAO K DTs s P V VV L DTs R RAMP MAX OUT IN OUT IN SENSE =− − µ {} − − − 22 11 1 1 22 2 18 () . () (1) OVERVOLTAGE PROTECTION AND INHIBIT The OVP pin serves to protect the power circuit from being subjected to excessive voltages if the load should change suddenly (lamp removal). A divider from the high voltage DC bus sets the OVP trip level. When the voltage on PVFB/OVP exceeds 2.75V, the PFC transistor are inhibited. The ballast section will continue to operate. 6 RSET RT/CT VCC VREF GND 2.5V PVFB/OVP PEAO CRAMP PIFB 7 RX/CX 9 16 17 11 18 1 10 2 OUT B 13 + – + – + – – + – + 2.5V 1.0V + – 1.25V –1.0V 2.75V PREHEAT TIMER OSC CLK UNDER-VOLTAGE THERMAL SHUTDOWN REFOK – + TQ PGND 12 OUT A 14 PFC OUT 15 PDWN 3 INTERRUPT 8 LFB OUT 5 LAMP FB 4 OVP ISENSE AMPLIFIER ILIM R SQ R S Q V TO I Figure 1. ML4833 Detailed Block Diagram |
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