ML6460

8

HSYNC

Line 3

Line 4

Line 5

Line 6

HSYNC

Line 265

Line 266

Line 267

Line 268

VSYNC

VSYNC

Beginning of

an Odd Field

Beginning of

an Even Field

Line 269

Coincident

Active Edges

Figure 1. Example of the Beginning of the Odd And Even Fields vs. HSYNC and VSYNC in Master Mode.

(SLAVE/MASTER = 0, SENSE_HSYNC = 0, SENSE_VSYNC

===== 0)

fields or as an output to monitor odd/even fields or analog

fields (1-2) and (3-4). The ML6460 also supports a frame

based synchronization mode (B17 = FSYNC = 1) where a

vertical reset pulse unconditionally resets the vertical line

counter to line 4. For proper operation only one active

edge should be sent per frame. The polarity is controlled

by SENSE_VSYNC (B10).