LC87F0N04A

No.A2055-3/19

Watchdog Timer

Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed

RC oscillation clock (30kHz).

Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/HOLD mode.

Interrupts

14 sources, 9 vector addresses

1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of

the level equal to or lower than the current interrupt are not accepted.

2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level

takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector

address takes precedence.

No.

Vector Address

Level

Interrupt Source

1

00003H

X or L

INT0

2

0000BH

X or L

INT1

3

00013H

H or L

INT2/T0L

4

0001BH

H or L

INT3/base timer

5

00023H

H or L

T0H

6

0002BH

H or L

T1L/T1H

7

00033H

H or L

-

8

0003BH

H or L

SIO1/PWM

9

00043H

H or L

ADC

10

0004BH

H or L

CMP1/CMP2

Priority levels X > H > L

Of interrupts of the same level, the one with the smallest vector address takes precedence.

Subroutine Stack Levels: 64levels (The stack is allocated in RAM.)

High-speed Multiplication/Division Instructions

16 bits  8 bits

(5 tCYC execution time)

24 bits  16 bits

(12 tCYC execution time)

16 bits  8 bits

(8 tCYC execution time)

24 bits  16 bits

(12 tCYC execution time)

Oscillation Circuits

Internal oscillation circuits

Medium-speed RC oscillation circuit : For system clock (1MHz)

High-speed RC oscillation circuit :

For system clock (10MHz)

Low-speed RC oscillation circuit :

For watch dog timer (30kHz)

System Clock Divider Function

Can run on low current.

The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and

76.8

s (at a main clock rate of 10MHz).

Internal Reset Function

Power-on reset (POR) function

1) POR reset is generated only at power-on time.

2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and

4.35V) through option configuration.

Low-voltage detection reset (LVD) function

1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls

below a certain level.

2) The use / disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V,

2.81V, 3.79V, 4.28V).