LC79451KB

No.A2223-11/38

5-6. SPI (3-wire serial interface) Timing Characteristics

(Case without the special mention VDD = +2.5V, VSS = 0V, Ta = +25°C)

Parameter

Symbol

Conditions

min

typ

max

Unit

VDD = 1.6V to 2.0V

-

-

6

MHz

SCL frequency

fSCL(2)

VDD = 2.0V to 3.6V

-

-

10

MHz

CS - SCL setup time

tSU(8)

300

-

-

ns

SCL - CS hold time

tHD(5)

300

-

-

ns

SDA - SCL setup time

tSU(9)

50

-

-

ns

SCL - SDA hold time

tHD(6)

50

-

-

ns

SCL low pulse width

tPW(4)

50

-

-

ns

SCL high pulse width

tPW(5)

50

-

-

ns

CS interval time

tINT(1)

1000

-

-

ns

1) SPI interface bus timing

Fig.7. SPI bus timing

2) Timing of BUSY and START Flag after setting START command in SPI interface

Output of BUSY means START Flag. During in BUSY=1, “WAVEFORM PARAMETER” and “CONTROL

REGISTER” are write inhibit state. An internal state is charge-pump rising period before the waveform output or

during the waveform output. After outputs waveform from segment, BUSY and START FLAG are automatically

canceled. (Cf. 6-3)

*1 Automatic charge-pump mode : charge-pump rising period (set to control register 1) + waveform

output period (set to waveform parameter)

Manual charge-pump mode :

waveform output period (set to waveform parameter)

*2 BUSY and START FLAG are automatically canceled.

Fig.8. SPI BUSY output, and START Flag timing

CS

SCL

tINT(1)

tHD(6)

SDA

tSU(8)

tHD(5)

tPW(4)

tPW(5)

tSU(9)

(A7)

(A6)

(D0)

(D1)

(10%)

(50%)

(50%)

(90%)

SCL

BUSY

*2

START Flag

*1

CS