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TECHNICAL DATA SHEET

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inventory and certifications: 60 GHz Receiver (Rx) Waveguide Module PEM002

PEM002

60 GHz Receiver (Rx) Waveguide Module

PEM002 REV

Digital Control Registers and Serial Interface Protocol - Write Operation

The PEM002 is configured via the serial control port which transfers data synchronously to or from (write or read operation)

a register location. Register locations are organized into 16, byte-wide (8-bit) locations. The register locations are written to

or read from one byte at a time as shown in Figures 5 and 6 respectively. Figure 5 shows the sequence of the digital control

signals for the ENABLE, CLOCK and DATA input pins (ST4 connector, pins 39, 36 and 38 respectively) to write a single byte

into the control register. After the ENABLE signal goes low, the first of 18 data bits (bit 0) is placed on the data pin, and 2

ns or more after the DATA signal stabilizes, the CLOCK signal goes high which clocks in data bit 0. The DATA signal must

remain stable for at least 2 ns after the rising edge of the CLOCK. The signal levels are 1.5V CMOS, 50 kΩ impedance, with

a maximum clock rate of 100 MHz.

A write operation requires an 18 bit field associated with 18 clock pulses as shown in Figure 5. The 18 bit field contains the

8-bit data (LSB is clocked in first), followed by the byte address (BYTE 0 through BYTE 15, 000000 to 001111, LSB first,

only 4 of the 6 bits are used with the two MSBs set to 0), the read/write (R/W) bit (write = 1), and the module address which

distinguishes between a transmitter module and receiver module (for the PEM002 receiver, RX module = 111).

After clock pulse 17 (18 total pulses), the ENABLE signal is returned to a high state to load the register byte into the module.

The CLOCK signal must be stable in the low state at least 2 ns prior to the rising edge of the ENABLE signal.

ENABLE

CLOCK

0

1

2

17

DATA

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17

Data

Byte Address

R/W TX/RX Module

Figure 5 Write Operation Timing Diagram