ATmega16 datasheet(68/315 Pages) ATMEL

68 / 315 page

ATmega16(L)

2466E–AVR–10/02

The double buffered Output Compare Register (OCR0) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the wave-

form generator to generate a PWM or variable frequency output on the Output Compare

Pin (OC0). See “Output Compare Unit” on page 69. for details. The compare match

event will also set the Compare Flag (OCF0) which can be used to generate an output

compare interrupt request.

Definitions

Many register and bit references in this document are written in general form. A lower

case “n” replaces the Timer/Counter number, in this case 0. However, when using the

accessing Timer/Counter0 counter value and so on.

The definitions in Table 37 are also used extensively throughout the document.

Timer/Counter Clock

Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock

source is selected by the clock select logic which is controlled by the clock select

(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on

clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on

page 81.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.

Figure 28 shows a block diagram of the counter and its surroundings.

Figure 28. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT0 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT0 (set all bits to zero).

clkTn

Timer/Counter clock, referred to as clkT0 in the following.

TOP

Signalize that TCNT0 has reached maximum value.

Table 37. Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest

value in the count sequence. The TOP value can be assigned to be the

fixed value 0xFF (MAX) or the value stored in the OCR0 register. The

assignment is dependent on the mode of operation.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int. Req.)

Clock Select

TOP

Edge

Detector

( From Prescaler )

clk

BOTTOM

direction

clear

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