3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-06052 Rev. *E
Revised October 12, 2004
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
•INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
Notes:
1.
I/O8–I/O15 for x16 devices; I/O9–I/O17 for x18 devices.
2.
I/O0–I/O7 for x16 devices; I/O0–I/O8 for x18 devices.
3.
A0–A11 for 4K devices; A0–A12 for 8K devices; A0–A13 for 16K devices.
4.
BUSY is an output in master mode and an input in slave mode.
R/WL
OEL
I/O8/9L–I/O15/17L
I/O
Control
Address
Decode
A0L–A11/12/13L
CEL
OEL
R/WL
BUSYL
I/O
Control
CEL
Interrupt
Semaphore
Arbitration
SEML
INTL
M/S
UBL
LBL
I/O0L–I/O7/8L
R/WR
OER
I/O8/9L–I/O15/17R
CER
UBR
LBR
I/O0L–I/O7/8R
UBL
LBL
Logic Block Diagram
A0L–A11/1213L
True Dual-Ported
RAM Array
A0R–A11/12/13R
CER
OER
R/WR
BUSYR
SEMR
INTR
UBR
LBR
Address
Decode
A0R–A11/12/13R
[1]
[1]
[2]
[2]
[4]
[4]
12/13/14
8/9
8/9
12/13/14
8/9
8/9
12/13/14
12/13/14
[3]
[3]
[3]
[3]
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