USB3803 datasheet(17/99 Pages) MICROCHIP

17 / 99 page

 2014-2015 Microchip Technology Inc.

DS00001691B-page 17

USB3803

4.2

Standby Mode

Standby Mode provides a very low power state for maximum power efficiency when no signaling is required. This is the

lowest power state. In Standby Mode all internal regulators are powered off, the bypass switch resistance is uncon-

strained, the PLL is not running, and core logic is powered down in order to reduce power. Because core logic is pow-

ered off, no configuration settings are retained in this mode and must be re-initialized after RESET_N is negated high.

4.2.1

EXTERNAL HARDWARE RESET_N

A valid hardware reset is defined as an assertion of RESET_N low for a minimum of 100us after all power supplies are

within operating range. While reset is asserted, the Hub (and its associated external circuitry) enters STANDBY MODE

and consumes extremely lowcurrent as defined in Table 10-3 and Table 10-4.

Assertion of RESET_N (external pin) causes the following:

• All downstream ports are disabled.

• The switch assumes resistance RSTDBY.

• All transactions immediately terminate; no states are saved.

• All internal registers return to the default state.

• The PLL is halted.

After RESET_N is negated high in the Hub.Init stage, the Hub reads customer-specific data from the ROM.

4.3

Bypass Mode (USB3803C Only)

Bypass Mode combines low power operation with the function of an integrated bypass switch. This mode allows a

bypass port (Downstream Port 3) to be electrically connected to the upstream port through use of a pass gate as illus-

trated in Figure 1-1. Compliant full speed USB signals may be successfully passed through the switch.

There are several applications for this mode. The bypass port can be used to provide connectivity to a PMIC to imple-

ment battery charger detection. In this configuration any special signaling is replicated on the line as if the hub were not

in series. Another application is for a downstream device on Port 3 to assume a full speed host role for an application

such as USB OTG or embedded usb host. It can also be used to provide audio signaling (must be offset to avoid neg-

ative signal swing.)

To insure that Bypass mode entered, RESET_N must be asserted and then de-asserted prior to asserting BYPASS_N

(refer to Table 4-1). In Bypass Mode the 1.2V regulator is powered off, PLL is not running and core logic is powered

down in order to reduce power. Because core logic is powered off, no configuration settings are retained in this mode

and must be re-initialized when BYPASS_N is negated to a high value.

4.3.1

VOLTAGE RANGE

The switch shall operate in a voltage range as specified by Vswitch in Table 10-9, “Analog Switch Characteristics,” on

page 83. Negative voltage swing is not supported.

4.3.2

SWITCH BANDWIDTH

The switch shall support compliant operation with an external full speed USB Port and with external battery charger

detection. Under certain conditions with short cables it may be possible to pass high speed USB signals. However, due

to physical design constraints, the switch is not necessarily intended to pass a fully compliant high speed USB eye.

4.4

Hub Mode

Hub Mode provides functions of configuration, upstream battery charger detection, and high speed USB hub operation

including connection and communication. Upon entering Hub Mode and initializing internal logic, the device passes

through several sequential stages based on a fixed time interval. In Hub Mode the bypass switch is disabled.

Note:

In order to adhere to the USB 2.0 Specification the system must not consume more than 100mA from the

upstream VBUS until the Hub is configured by the host.

USB3803 Datasheet(PDF) 17 Page - Microchip Technology

USB3803 Datasheet(HTML) 17 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

Datasheet Download

Link URL