USB3320 datasheet(46/70 Pages) MICROCHIP

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USB3320

DS00001792B-page 46

 2014-2015 Microchip Technology Inc.

6.4.1

3PIN FS/LS SERIAL MODE

Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-5.

6.4.2

6PIN FS/LS SERIAL MODE

Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6-6.

6.5

Carkit Mode

The USB3320 includes Carkit Mode to support a USB UART and USB Audio Mode.

By entering Carkit Mode, the USB3320 current drain is minimized. When operating in ULPI Input Clock Mode (60MHz

REFCLK Mode), the CLKOUT is stopped to conserve power by default. The Link may configure the 60MHz clock to

continue by setting the ClockSuspendM bit of the Interface Control register before entering Carkit Mode. If set, the 60

MHz clock will continue during the Carkit Mode of operation.

In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register. The state of

each interrupt source is sampled prior to the assertion of DIR and this is compared against the asynchronous level from

interrupt source. In Carkit Mode, the Linestate signals are not available per the ULPI specification.

Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.3.2. The Link must assert STP

to signal the transceiver to exit serial mode. When the transceiver can accept a command, DIR is de-asserted and the

transceiver will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can also

be pulsed low to reset the USB3320 and return it to Synchronous Mode.

6.5.1

USB UART MODE

The USB3320 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit Control register.

Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn and RxdEn bits must be written

before the CarkitMode bit.

TABLE 6-5:

PIN DEFINITIONS IN 3 PIN SERIAL MODE

Signal

Connected To

Direction

Description

tx_enable

DATA[0]

Active High transmit enable.

data

DATA[1]

I/O

TX differential data on DP/DM when tx_enable is high.

RX differential data from DP/DM when tx_enable is low.

SE0

DATA[2]

I/O

TX SE0 on DP/DM when tx_enable is high.

RX SE0_b from DP/DM when tx_enable is low.

interrupt

DATA[3]

OUT

Asserted when any unmasked interrupt occurs. Active high.

Reserved

DATA[7:4]

OUT

Driven Low.

TABLE 6-6:

PIN DEFINITIONS IN 6 PIN SERIAL MODE

Signal

Connected To

Direction

Description

tx_enable

DATA[0]

Active High transmit enable.

tx_data

DATA[1]

Tx differential data on DP/DM when tx_enable is high.

tx_se0

DATA[2]

Tx SE0 on DP/DM when tx_enable is high.

interrupt

DATA[3]

OUT

Asserted when any unmasked interrupt occurs. Active high.

rx_dp

DATA[4]

OUT

Single ended receive data on DP.

rx_dm

DATA[5]

OUT

Single ended receive data on DM.

rx_rcv

DATA[6]

OUT

Differential receive data from DP and DM.

Reserved

DATA[7]

OUT

Driven Low.

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