M95040-DRMF3TP datasheet(12/41 Pages) STMICROELECTRONICS

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Operating features

M95040-A125 M95040-A145

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DocID024225 Rev 6

3.4.2

Status Register and data protection

The Status Register format is shown in Table 2 and the status and control bits of the Status

Note:

Bits b7, b6, b5 and b4 are always read as 1.

WIP bit

The WIP bit (Write In Progress) is a read-only flag that indicates the Ready/Busy state of the

device. When a Write command (WRITE, WRSR, WRID, LID) has been decoded and a

Write cycle (tW) is in progress, the device is busy and the WIP bit is set to 1. When WIP=0,

the device is ready to decode a new command.

During a Write cycle, reading continuously the WIP bit allows to detect when the device

becomes ready (WIP=0) to decode a new command.

WEL bit

The WEL bit (Write Enable Latch) bit is a flag that indicates the status of the internal Write

Enable Latch. When WEL is set to 1, the Write instructions (WRITE, WRSR, WRID, LID) are

executed; when WEL is set to 0, any decoded Write instruction is not executed.

The WEL bit is set to 1 with the WREN instruction. The WEL bit is reset to 0 after the

following events:

•

Write Disable (WRDI) instruction completion

•

Write instructions (WRITE, WRSR, WRID, LID) completion including the write cycle

time tW

•

Power-up

BP1, BP0 bits

The Block Protect bits (BP1, BP0) are non-volatile. BP1,BP0 bits define the size of the

memory block to be protected against write instructions, as defined in Table 2. These bits

are written with the Write Status Register (WRSR) instruction.

Table 2. Status Register format

BP1

BP0

WEL

WIP

Block Protect bits

Write Enable Latch bit

Write In Progress bit

M95040-DRMF3TP Datasheet(PDF) 12 Page - STMicroelectronics