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VNI8200XP-32 Datasheet(PDF) 20 Page - STMicroelectronics

Part # VNI8200XP-32
Description  Octal high-side smart power solid-state relay with serial
PDF  43 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

VNI8200XP-32 Datasheet(HTML) 20 Page - STMicroelectronics

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Pin function description
VNI8200XP-32
20/43
DocID027849 Rev 3
9
Pin function description
9.1
SPI/parallel selection mode (SEL2)
This pin allows the selection of the IC interfacing mode. The SPI interface is selected if
SEL2 = H, while the parallel interface is selected if SEL2 = L, according to :
Table 13: Pin function description
Pin
SEL2 = H
a
SPI operation
SEL2 = L
parallel operation
SDO/IN8
SDO
Serial data output
IN8
Input to channel 8
SS /IN7
SS
Slave select
IN7
Input to channel 7
CLK/IN6
CLK
Serial clock
IN6
Input to channel 6
SDI/IN5
SDI
Serial data input
IN5
Input to channel 5
WD/IN4
WD
Watchdog input
IN4
Input to channel 4
OUT_EN/IN3
OUT_EN
IC OUTPUT enable / disable
IN3
Input to channel 3
WD_EN/IN2
WD_EN
Watchdog enable / disable and timing preset
IN2
Input to channel 2
SEL1/IN1
SEL1
8/16-bit SPI selection mode
IN1
Input to channel 1
9.2
Serial data in (SDI)
If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges
and, therefore, the microcontroller must change SDI state during the CLK falling edges.
After the SS
falling edge, the SDI is equal to the most significant bit of the control frame
(Figure 5: "SPI mode diagram").
9.3
Serial data out (SDO)
If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling
edges and, therefore, the microcontroller must read SDO state during the CLK rising
edges.
The SDO pin is tri-stated when SS
signal is high and it is equal to the most significant bit
of the fault frame after the SS
falling edge (Figure 5: "SPI mode diagram").
9.4
Serial data clock (CLK)
If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the
SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller.
On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from
the most to the less significant one (see Figure 5: "SPI mode diagram"). When the SS
a
SEL2 has an internal weak pull-down.



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