17

Aeroflex Microelectronics Solutions - HiRel

36-00-00-001

Ver. 1.5.0

3.2 Recommended Operating Conditions

3.3 Operational Environmet

The UT699E processor includes the following SEU mitigation features:

* Cache memory error-detection of up to 4 errors per tag or 32-bit word

* Autonomous and software transparent error handling

* No timing impact due to error detection or correction

Notes:

1. TID irradation per MIL-STD-883, Test Method 1019, condition A. Post irradiation electrical testing performed at room temperature.

3. Contact factory for error rate information.

4. The error rate calculation was performed using SpaceRad 6.0 for a Geosynchronous orbit in the Adams 90% worst-case environment with 100mil Al

shielding.

Symbol

Description

Min

Max

Units

Core supply voltage

1.1

1.3

V

I/O supply voltage

3.0

3.6

V

Input voltage any pin

0

V

Case operating temperature

-55

105

Rise time, all CMOS and PCI inputs

--

20

ns

Fall time, all CMOS and PCI inputs

--

20

ns

PARAMETER

LIMIT

UNITS

1E5

rad (Si)

<110

Inherent register upset rate

5.2E-7

errors/device-day

Multiple-bit error (MBE) rate which over-

comes internal error detection & correction

architecture

2.8E-11

MBE/device-day