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UT54ACTS220 Datasheet(PDF) 1 Page - Aeroflex Circuit Technology |
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UT54ACTS220 Datasheet(HTML) 1 Page - Aeroflex Circuit Technology |
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1 / 12 page  1 Standard Products UT54ACTS220 Clock and Wait-State Generation Circuit Datasheet November 2010 www.aeroflex.com/logic FEATURES 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack UT54ACTS220 - SMD 5962-96753 DESCRIPTION The UT54ACTS220 is designed to be a companion chip to UTMC’s UT69151 S μMMIT family for the purpose of gener- ating clock and wait-state signals. The device contains a divide by two circuit that accepts TTL input levels and drives CMOS output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit generates a single wait-state by delaying the falling edge of DTACK into the S μMMIT. The clock/timing device generates DTACK from the falling edge of input RCS which is synchronized by the fall- ing edge of 24MHz. The S μMMIT drives inputs RCS and DMACK. The devices are characterized over full military temperature range of -55 °C to +125°C. LOGIC SYMBOL PINOUTS 14-Pin DIP Top View 14-Lead Flatpack Top View (10) MRST (8) DMACK (6) 48MHz (9) RCS (13) 24MHz (11) (12) DTACK (4) CLKIN (2) CLKOUT (3) CLKOUT S CTR1 SRG2 1D S TEST Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 114 213 312 411 510 69 78 NC CLKOUT CLKOUT CLKIN NC 48MHz VSS VDD 24MHz DTACK MRST RCS DMACK TEST 114 213 312 411 510 69 78 NC CLKOUT CLKOUT CLKIN NC 48MHz VSS VDD 24MHz DTACK MRST RCS DMACK TEST |
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