SP502 datasheet(8/32 Pages) SIPEX

8 / 32 page

Rev. 7/21/03

SP502 Multi-Mode Serial Transceiver

FEATURES…

The SP502 is a highly integrated serial trans-

ceiver that allows software control of its inter-

face modes. The SP502 offers hardware inter-

face modes for RS-232 (V.28), RS-422A (V.11),

RS-449, RS-485, V.35, and EIA-530. The inter-

face mode selection is done via an 8–bit switch;

four (4) bits control the drivers and four (4) bits

control the receivers. The SP502 is fabricated

using low–power BiCMOS process technology,

and incorporates a Sipex patented (5,306,954)

charge pump allowing +5V only operation. Each

THEORY OF OPERATION

Charge–Pump

The charge pump is a Sipex patented design

(5,306,954) and uses a unique approach com-

pared to older less efficient designs. The charge

pump still requires four external capacitors, but

uses a four–phase voltage shifting technique to

attain symmetrical 10V power supplies. Figure

3a shows the waveform found on the positive

side of capcitor C

2, and Figure 3b shows the

negative side of capcitor C

2. There is a free–

running oscillator that controls the four phases

of the voltage shifting. A description of each

phase follows.

Phase 1

— V

SS charge storage —During this phase of

the clock cycle, the positive side of capacitors

1 and C2 are initially charged to +5V. Cl

+ is

then switched to ground and the charge on C

–

is transferred to C

–. Since C

+ is connected

to +5V, the voltage potential across capacitor

2 is now 10V.

Phase 2

— V

SS transfer — Phase two of the clock con-

nects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V to

3. Simultaneously, the positive side of capaci-

Pin 78 — DSR— Data Set Ready; TTL output;

sourced from DM(a), DM(b) inputs.

Pin 80 — CTS— Clear To Send; TTL output;

sourced from CS(a) and CS(b) inputs.

CONTROL REGISTERS

Pins 2–5 — RDEC0 – RDEC3 — Receiver

decode register; configures receiver modes; TTL

inputs.

Pin 6 — ST/TT — Enables ST or TT drivers,

TTL input.

Pins 12–9 — TDEC0 – TDEC3 — Transmitter

decode register; configures transmitter modes;

TTL inputs.

POWER SUPPLIES

Pins 8, 25, 33, 41, 48, 55, 62, 73, 74 — V

CC —

+5V input.

Pins 7, 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75

— GND — Ground.

Pin 27 — V

DD +10V Charge Pump Capacitor —

Connects from V

DD to VCC. Suggested capaci-

tor size is 22

µF, 16V.

Pin 32 — V

SS –10V Charge Pump Capacitor —

Connects from ground to V

SS.

Suggested ca-

pacitor size is 22

µF, 16V.

Pins 26 and 30 — C

+ and C

– — Charge Pump

Capacitor — Connects from C

+ to C

–. Sug-

gested capacitor size is 22

µF, 16V.

Pins 28 and 31 — C

+ and C

– — Charge Pump

Capacitor — Connects from C

+ to C

–. Sug-

gested capacitor size is 22

µF, 16V.

NOTE: NC pins should be left floating; internal

signals may be present.

device is packaged in an 80–pin Quad FlatPack

package.

The SP502 is ideally suited for wide area net-

work connectivity based on the interface modes

offered and the driver and receiver configura-

tions. The SP502 has five (5) independent driv-

ers and six (6) independent receivers and one

half–duplex transceiver channel, which allows

a maximum of six (6) drivers and seven (7)

receivers. The driver and receiver configuration

for the SP502 is ideal for DTE applications. The

SP502 is made up of four separate circuit blocks

– the charge pump, drivers, receivers, and

decoder. Each of these circuit blocks is de-

scribed in detail below.

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