SP505AB datasheet(19/36 Pages) SIPEX

19 / 36 page

Rev. 7/9/03

SP505 Multi–Mode Serial Transceiver

Phase 2 (±10V)

— V

SS transfer — Phase two of the clock con-

nects the negative terminal of C

2 to the VSS

storage capacitor and the positive terminal of C

to ground, and transfers the generated –l0V or

the generated –5V to C

3. Simultaneously, the

positive side of capacitor C

1 is switched to +5V

and the negative side is connected to ground.

Phase 2 (±5V)

— V

SS & VDD charge storage — C1

+ is recon-

nected to V

CC to recharge the C1 capacitor. C2

is switched to ground and C

– is connected to C

The 5V charge from Phase 1 is now transferred

to the V

SS storage capacitor.

SS receives a

continuous charge from either C

1 or C2. With

the C1 capacitor charged to 5V, the cycle begins

again.

Phase 3

— V

DD charge storage — The third phase of the

clock is identical to the first phase — the charge

transferred in C

1 produces –5V in the negative

terminal of C

1, which is applied to the negative

side of capacitor C

2. Since C2

+ is at +5V, the

voltage potential across C

2 is l0V. For the 5V

output, C

+ is connected to ground so that the

potential on C

2 is only +5V.

Phase 4

— V

DD transfer — The fourth phase of the

clock connects the negative terminal of C

2 to

ground and transfers the generated l0V or the

generated 5V across C

2 to C4, the VDD storage

capacitor. Again, simultaneously with this, the

positive side of capacitor C

1 is switched to +5V

and the negative side is connected to ground,

and the cycle begins again.

Since both V

DD and VSS are separately gener-

ated from V

CC in a no–load condition, VDD and

SS will be symmetrical. Older charge pump

approaches that generate V– from V+ will show

a decrease in the magnitude of V– compared to

V+ due to the inherent inefficiencies in the

design.

The clock rate for the charge pump typically

operates at 15kHz. The external capacitors must

be a minimum of 22

µF with a 16V breakdown

rating.

External Power Supplies

For applications that do not require +5V only,

external supplies can be applied at the V+ and

V– pins. The value of the external supply volt-

ages must be no greater than +l0.5V. The toler-

ance should be +5% from +10V. The current

drain for the supplies is used for RS-232 and RS-

423 drivers. For the RS-232 driver, the current

requirement will be 3.5mA per driver. The RS-

423 driver worst case current drain will be

11mA per driver. Power sequencing is required

for the SP505. The supplies must be sequenced

accordingly: +10V, +5V and –10V. It is impor-

tant to prevent V

SS from starting up before VCC

or V

DD.

Figure 47. Charge Pump Phase 2 for +10V.

Figure 49. Charge Pump Phase 3.

VCC = +5V

–10V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

VCC = +5V

–5V

+5V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

Figure 50. Charge Pump Phase 4.

Figure 48. Charge Pump Phase 2 for +5V.

VCC = +5V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

–5V

VCC = +5V

+10V

VDD Storage Capacitor

–

VSS Storage Capacitor

–

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