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DSP56362AD Datasheet(PDF) 16 Page - Motorola, Inc

Part # DSP56362AD
Description  24-Bit Audio Digital Signal Processor
PDF  168 Pages
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

DSP56362AD Datasheet(HTML) 16 Page - Motorola, Inc

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1-8
DSP56362 Advance Information
MOTOROLA
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
BR
Output
Output
(deasserted)
Bus Request—BR is an active-low output, never tri-
stated. BR is asserted when the DSP requests bus
mastership. BR is deasserted when the DSP no longer
needs the bus. BR may be asserted or deasserted
independent of whether the DSP56362 is a bus master
or a bus slave. Bus “parking” allows BR to be deasserted
even though the DSP56362 is the bus master. (See the
description of bus “parking” in the BB signal description.)
The bus request hold (BRH) bit in the BCR allows BR to
be asserted under software control even though the DSP
does not need the bus. BR is typically sent to an external
bus arbitrator that controls the priority, parking, and
tenure of each master on the same external bus. BR is
only affected by DSP requests for the external bus, never
for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave
state.
BG
Input
Ignored Input
Bus Grant—BG is an active-low input. BG is asserted by
an external bus arbitration circuit when the DSP56362
becomes the next bus master. When BG is asserted, the
DSP56362 must wait until BB is deasserted before taking
bus mastership. When BG is deasserted, bus mastership
is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that
requires more than one external bus cycle for execution.
The default mode of operation of this signal requires a
setup and hold time referred to CLKOUT. But CLKOUT
operation is not guaranteed from 100MHz and up, so the
asynchronous bus arbitration must be used for clock
frequencies 100MHz and above. The asynchronous bus
arbitration is enabled by setting the ABE bit in the OMR
register.
Table 1-7 External Bus Control Signals (Continued)
Signal
Name
Type
State during
Reset
Signal Description
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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