ICS93732 datasheet(1/8 Pages) ICST

Part #	ICS93732

Description	Low Cost DDR Phase Lock Loop Zero Delay Buffer

PDF	8 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 8 page

Integrated

Circuit

Systems, Inc.

ICS93732

0578H—02/19/04

Block Diagram

Low Cost DDR Phase Lock Loop Zero Delay Buffer

Pin Configuration

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

•

Low skew, low jitter PLL clock driver

•

Max frequency supported = 266MHz (DDR 533)

•I

2C for functional and output control

•

Feedback pins for input to output synchronization

•

Spread Spectrum tolerant inputs

•

3.3V tolerant CLK_INT input

Switching Characteristics:

•

CYCLE - CYCLE jitter (66MHz): <120ps

•

CYCLE - CYCLE jitter (>100MHz): <65ps

•

CYCLE - CYCLE jitter (>200MHz): <75ps

•

OUTPUT - OUTPUT skew: <100ps

•

DUTY CYCLE: 49.5% - 50.5%

Functionality

S

T

U

P

N

IS

T

U

P

T

U

O

e

t

a

t

S

L

P

D

V

AT

N

I

_

K

L

CT

K

L

CC

K

L

CT

T

U

O

_

B

F

V

5

.

2

)

m

o

n

(

LL

H

L

n

o

V

5

.

2

)

m

o

n

(

HH

L

H

n

o

FB_INT

CLK_INT

SCLK

SD

SDA

AT

TA

A

Control

Logic

FB_OUTT

DDRC0

PLL

DDRT0

DDRC1

DDRT1

DDRC2

DDRT2

DDRC3

DDRT3

DDRC4

DDRT4

DDRC5

DDRT5

DDRC0

1

28 GND

DDRT0

2

27 DDRC5

VDD

3

26 DDRT5

DDRT1

4

25 DDRC4

DDRC1

5

24 DDRT4

GND

6

23 VDD

SCLK

7

22 SDATA

CLK_INT

8

21 N/C

N/C

9

20 FB_INT

VDDA 10

19 FB_OUT

GND 11

18 N/C

VDD 12

17 DDRT3

DDRT2 13

16 DDRC3

DDRC2 14

15 GND

28-Pin 209mil SSOP

28-Pin 173mil TSSOP

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