DP8228 datasheet(5/6 Pages) NSC

5 / 6 page

Functional Pin Definitions (Continued)

tion between the CPU memory and inputoutput devices

for instructions and data transfers A status word (which de-

scribes the current machine cycle) is also outputted on this

data bus during the first microcycle of each machine cycle

(SYNC e logic 1)

System Data (DB7–DB0) Bus This bus comprises eight

TRI-STATE inputoutput lines that connect to the memory

and inputoutput components of the system The internal

bidirectional bus driver isolates the DB7–DB0 Data Bus from

the D7–D0 Data Bus

Status Word Chart

Machine Cycle

Status

Data Bus Bit

Control

Word

Signal

Instruction Fetch

MEMR

Memory Read

MEMR

Memory Write

MEMW

Stack Read

MEMR

Stack Write

MEMW

Input Read

IOR

Output Write

IOW

Interrupt Acknowledge

INTA

Halt Acknowledge

(none)

Interrupt Acknowledge While Halt

INTA

Block and Connection Diagrams

TLF6825 – 6

Dual-In-Line Package

TLF6825 – 7

Order Number DP8228J DP8228MJ

DP8228N DP8238J DP8238MJ or

DP8238N

See NS Package Number J28A or N28B

DP8228 Datasheet(PDF) 5 Page - National Semiconductor (TI)

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