AD6635BBSLASHPCB datasheet(49/60 Pages) AD

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Table XV. Memory Map for Output Port Control Registers (continued)

Channel Address (hex)

Bit Width

Comments

3: Channel 2

2: Channel 1/AGC B Enable

1: Channel 0/AGC A Enable

0: AGC_CH Select

1: Data Comes from AGCs

0: Data Comes from Channels

Link A Control

7: Link Port A Enable

6–3: Wait

2: No RSSI Word

1: Don’t Output RSSI Word

0: Output RSSI Word

1: Channel Data Interleaved

1: 2-Channel Mode/Separate A, B

0: 4-Channel Mode/A, B Same Port

0: AGC_CH Select

1: Data Comes from AGCs

0: Data Comes from Channels

Parallel B Control

7–6: Reserved

5: Parallel Port Data Format

1: 8-Bit Parallel I, Q

0: 16-Bit Interleaved I, Q

4: Channel 3

3: Channel 2

2: Channel 1/AGC B Enable

1: Channel 0/AGC A Enable

0: AGC_CH Select

1: Data Comes from AGCs

0: Data Comes from Channels

Link B Control

7: Link Port A Enable

6–3: Wait

2: No RSSI Word

1: Don’t Output RSSI Word

0: Output RSSI Word

1: Channel Data Interleaved

1: 2-Channel Mode/Separate A, B

0: 4-Channel Mode/A, B Same Port

0: AGC_CH Select

1: Data Comes from AGCs

0: Data Comes from Channels

Port Clock Control

2–1: PCLK Divisor

0: PCLK Master/Slave1

0: Slave

1: Master

1PCLK boots as slave to avoid contention.

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