REV. 0

–4–

AD8328

ABSOLUTE MAXIMUM RATINGS

*

Input Voltage

VIN+, VIN– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V p-p

DATEN, SDATA, CLK,

SLEEP, TXEN . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V

Internal Power Dissipation

QSOP, LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mW

Operating Temperature Range . . . . . . . . . . . –40

°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300

°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD8328 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

ORDERING GUIDE

Model

Temperature Range

Package Description

θ

JA

Package Option

AD8328ARQ

–40

°C to +85°C

20-Lead QSOP

83.2

RQ-20

AD8328ARQ-REEL

–40

°C to +85°C

20-Lead QSOP

83.2

RQ-20

AD8328ARQ-EVAL

Evaluation Board

AD8328ACP

–40

°C to +85°C

20-Lead LFCSP

30.4

CP-20

AD8328ACP-REEL

–40

°C to +85°C

20-Lead LFCSP

30.4

CP-20

AD8328ACP-EVAL

Evaluation Board

20-Lead

QSOP

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

1

2

3

4

5

6

7

8

9

10

AD8328

TXEN

SDATA

CLK

SLEEP

BYP

NC

NC = NO CONNECT

GND

GND

GND

GND

RAMP

GND

DATEN

GND

20-Lead

LFCSP

TOP VIEW

(Not to Scale)

AD8328

1

2

3

4

5

15

14

13

12

11

16

17

20 19 18

6

789

10

GND

GND

GND

RAMP

BYP

NC

PIN FUNCTION DESCRIPTIONS

Pin No.

Pin No.

20-Lead

20-Lead

LFCSP

QSOP

Mnemonic

Description

1 ,2, 5,

1, 3, 4, 7,

GND

Common External Ground Reference

9, 18, 19

11, 20

17, 20

2, 19

Common Positive External Supply Voltage. A 0.1

µF capacitor must decouple each pin.

35

µF capacitor.

46

µF capacitor.

68

DATEN

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1

transition transfers the latched data to the attenuator core (updates the gain) and simultaneously

inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous

gain state) and simultaneously enables the register for serial data load.

79

SDATA

Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal

register with the MSB (most significant bit) first.

810CLK

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave

register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.

This requires the input serial data-word to be valid at or before this clock transition.

10

12

SLEEP

Low Power Sleep Mode. In the Sleep mode, the AD8328’s supply current is reduced to 20

µA. A Logic 0

12

14

BYP

Internal Bypass. This pin must be externally ac-coupled (0.1

µF capacitor).

13

15

Negative Output Signal

14

16

Positive Output Signal

15

17

RAMP

External RAMP Capacitor (optional)

16

18

TXEN

Logic 0 disables forward transmission. Logic 1 enables forward transmission.