50 Pin Descriptions

Pin No

Name

IO

Description

O

Collision Output

Balanced differential line driver outputs from the collision detect

circuitry The 10 MHz signal from the internal oscillator is transferred to these

outputs in the event of collision excessive transmission (jabber) or during CD

Heartbeat condition These outputs are open emitters pulldown resistors to VEE

are required When operating into a 78X transmission line these resistors should

be 500X In Cheapernet applications where the 78X drop cable is not used

higher resistor values (up to 15k) may be used to save power

O

Receive Output

Balanced differential line driver outputs from the Receiver These

outputs also require 500X pulldown resistors

I

Transmit Input

Balanced differential line receiver inputs to the Transmitter The

common mode voltage for these inputs is determined internally and must not be

externally established Signals meeting Transmitter squelch requirements are

waveshaped and output at TXO

9

HBE

I

Heartbeat Enable

This input enables CD Heartbeat when grounded disables it

when connected to VEE

11

I

External Resistor

A fixed 1k 1% resistor connected between these pins

establishes internal operating currents

12

14

RXI

I

Receive Input

Connects directly to the coaxial cable Signals meeting Receiver

squelch requirements are equalized for inter-symbol distortion amplified and

15

TXO

O

Transmit Output

Connects either directly (Cheapernet) or via an isolation diode

(Ethernet) to the coaxial cable

16

CDS

I

Collision Detect Sense

Ground sense connection for the collision detect circuit

This pin should be connected separately to the shield to avoid ground drops from

altering the receive mode collision threshold

10

GND

Positive Supply Pin

A 01 mF ceramic decoupling capacitor must be connected

across GND and VEE as close to the device as possible

4

VEE

Negative Supply Pins

In order to make full use of the 35W power dissipation

capability of this package these pins should be connected to a large metal frame

5

area on the PC board Doing this will reduce the operating die temperature of the

13

device thereby increasing the long term reliability

51 PC BOARD LAYOUT

The DP8392A package is uniquely designed to ensure that

the device meets the 1 million hour Mean Time Between

Failure (MTBF) requirement of the IEEE 8023 standard In

order to fully utilize this heat dissipation design the three

should be included in the printed circuit board layout Refer

to National Semiconductor application note AN-442 (Ether-

netCheapernet Physical Layer Made Easy) for complete

board layout instructions

5