DP83950B datasheet(49/80 Pages) NSC

49 / 80 page

60 Hub Management Support (Continued)

Packet Status Register 2

OWC

NSFD

PLER

ELBER

JAB

CBT9

CBT8

Bit

Symbol

Description

D(10)

CT(98)

COLLISION TIMER BITS 9 AND 8

These two bits are the upper bits of the collision bit timer

JAB

JABBER EVENT

This bit indicates that the receive packet was so long the repeater was forced to go into a

jabber protect condition

ELBER

ELASTICITY BUFFER ERROR

During the packet an Elasticity Buffer underoverflow occurred

PLER

PHASE LOCK LOOP ERROR

The packet suffered sufficient jitternoise corruption to cause the phase

lock loop decoder to lose lock

NSFD

NON SFD

The repeated packet did not contain a Start of Frame Delimiter When this bit is set the Repeat

Byte Counter counts the length of the entire packet When this bit is not set the byte counter only counts

post SFD bytes

Note

The operation of this bit is not inhibited by the occurrence of a collision during packet repetition (see description of the

Repeat Byte Counter below)

OWC

OUT OF WINDOW COLLISION

The packet suffered an out of window collision

SHORT EVENT

The receive activity was so small it met the criteria to be classed as a short event

The other registers comprise the remainder of the collision

timer register PSR(3)

the Repeat Byte Count registers

PSR(4) (5) and the Inter Frame Gap Counter ‘‘IFG’’ regis-

ter PSR(6)

Collision Bit Timer

The Collision Timer counts in bit times the time between the

start of repetition of the packet and the detection of the

packet’s first collision The Collision counter increments as

the packet is repeated and freezes when a collision occurs

The value in the counter is only valid when the collision bit

‘‘COL’’ in PSR(1) is set

Repeat Byte Counter

The Repeat Byte Counter is a 16 bit counter which can per-

form two functions In cases where the transmitted packet

possesses an SFD the byte counter counts the number of

received bytes after the SFD field Alternatively if no SFD is

repeated the counter reflects the length of the packet

counted in bytes starting at the beginning of the preamble

field When performing the latter function the counter is

shortened to 7 bits Thus the maximum count value is 127

bytes The mode of counting is indicated by the ‘‘NSFD’’ bit

in PSR(2)

In order to check if the received packet was

genuinely a Non-SFD packet the status of the COL bit

should be checked During collisions SFD fields may be lost

or created Management software should be robust to this

kind of behaviour

Inter Frame Gap (IFG) Bit Timer

The IFG counter counts in bit times the period in between

repeater transmissions The IFG counter increments when-

ever the RIC is not transmitting a packet If the IFG is long

greater than 255 bits the counter sticks at this value

Thus an apparent count value of 255 should be interpreted

as 255 or more bit times

64 DESCRIPTION OF HARDWARE

CONNECTION FOR MANAGEMENT INTERFACE

The RIC has been designed so it may be connected to the

Management bus directly or via external bus transceivers

The latter is advantageous in large repeaters In this appli-

cation the system backplane is often heavily loaded beyond

the drive capabilities of the on-chip bus drivers

The uni-directional nature of information transfer on the

MCRS MRXD and MRXC signals means a single open

drain output pin is adequate for each of these signals The

Management Enable (MEN) RIC output pin performs the

function of a drive enable for an external bus transceiver if

one is required

In common with the Inter-RIC bus signals ACTN ANYXN

COLN and IRE the MCRS active level asserted by the

MCRS output is determined by the state of the BINV Mode

Load configuration bit

70 Port Block Functions

The RIC has 13 port logic blocks (one for each network

connection) In addition to the packet repetition operations

already described the port block performs two other func-

tions

1 The physical connection to the network segment (trans-

ceiver function)

2 It provides a means to protect the network from malfunc-

tioning segments (segment partition)

Each port has its own status register This register allows

the user to determine the current status of the port and

configure a number of port specific functions

DP83950B Datasheet(PDF) 49 Page - National Semiconductor (TI)

DP83950B Datasheet(HTML) 49 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL