A1

B1

C1

A3

B3

C3

SW

A2

C2

EN

PGND

SGND

FB

A3

B3

C3

A1

B1

C1

A2

C2

SW

PGND

SGND

FB

EN

Top View

Bottom View

LM3208

SNVS404B – APRIL 2006 – REVISED MARCH 2013

www.ti.com

CONNECTION DIAGRAMS

Figure 2. 8-Bump Thin DSBGA Package, Large Bump

Package Number YZR0008GNA

PIN DESCRIPTIONS

Pin #

Name

Description

A1

Power Supply Voltage Input to the internal PFET switch.

B1

Analog Supply Input.

C1

EN

Enable Input. Set this digital input high for normal operation. For shutdown, set this pin low.

C2

C3

FB

Feedback Analog Input. Connect to the output at the output filter capacitor.

B3

SGND

Analog and Control Ground

A3

PGND

Power Ground

A2

SW

Switch node connection to the internal PFET switch and NFET synchronous rectifier.

Connect to an inductor with a saturation current rating that exceeds the maximum Switch Peak Current Limit

specification of the LM3208.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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