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LP3907QTLX-VXSS/NOPB Datasheet(PDF) 21 Page - Texas Instruments |
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LP3907QTLX-VXSS/NOPB Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 53 page ![]() LP3907-Q1 www.ti.com SNVSA55A – DECEMBER 2014 – REVISED MAY 2015 Table 6. Power-Off Timing Specification DESCRIPTION MIN NOM MAX UNIT t1 Programmable Delay from EN_T deassertion to VCC_Buck1 Off 1.5 ms t2 Programmable Delay from EN_T deassertion to VCC_Buck2 Off 2 ms t3 Programmable Delay from EN_T deassertion to VCC_LDO1 Off 3 ms t4 Programmable Delay from EN_T deassertion to VCC_LDO2 Off 6 ms 8.3.3 Flexible Power-On Reset (Power Good with Delay) The LP3907-Q1 is equipped with an internal Power-On-Reset (POR) circuit which monitors the output voltage levels on Bucks 1 and 2. The nPOR is an open drain logic output which is logic LOW when either of the buck outputs are below 91% of the rising value , or when one or both outputs fall below 82% of the desired value. The time delay between output voltage level and nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms) 50 ms by default. The system designer can choose the external pull-up resistor (that is, 100 k Ω) for the nPOR pin. Copyright © 2014–2015, Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links: LP3907-Q1 |
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