CLC5902 datasheet(18/28 Pages) NSC

18 / 28 page

Rev. 3.05 May 27, 1999

Output Modes

After processing by the DDC, the data is then formatted

for output.

Note

All output data is two’s complement.

Output formats include truncation to 8 or 32 bits, rounding

to 16 or 24 bits, and a 12-bit floating point format (4-bit

exponent, 8-bit mantissa, 138dB numeric range). This

function is performed in the OUTPUT CIRCUIT shown in

Figure 28.

The channel outputs are accessible through serial output

pins and a 16-bit parallel output port. The RDY pin is pro-

vided to notify the user that a new output sample period

(OSP) has begun. OSP refers to the interval between out-

put samples at the decimated output rate. For example, if

the input rate (and clock rate) is 52 MHz and the overall

decimation factor is 192 (N=48, F2 decimation=2) the

OSP will be 3.69 microseconds which corresponds to an

output sample rate of 270.83kHz. An OSP starts when a

sample is ready and stops when the next one is ready.

Note

The serial outputs power up in a tri-state

condition and must be enabled when the chip

is configured. Parallel outputs are enabled by

the POUT_EN pin.

Serial Outputs

The CLC5902 provides a serial clock (SCK), a frame

strobe (SFS) and two data lines (AOUT and BOUT) to

output serial data. The MUX_MODE control register

specifies whether the two channel outputs are transmitted

on two separate serial pins, or multiplexed onto one pin in

a time division multiplexed (TDM) format. Separate out-

put pins are not provided for the I and Q halves of com-

plex data. The I and Q outputs are always multiplexed

onto the same serial pin. The I-component is output first,

followed by the Q-component. By setting the PACKED

mode bit to ‘1’ a complex pair may be treated as a single

double-wide word. The RDY signal is used to identify the

first word of a complex pair of the TDM formatted output.

The TDM modes are summarized in Table 2.

The serial outputs use the format shown in Figure 29. Fig-

ure 29(a) shows the standard output mode (the PACKED

mode bit is low). The chip clocks the frame and data out of

the chip on the rising edge of SCK (or falling edge if the

SCK_POL bit in the input control register is set high).

Data should be captured on the falling edge of SCK (ris-

ing if SCK_POL=1). The chip sends the I data first by set-

ting SFS high (or low if SFS_POL in the input control

ting the data, MSB first, on as many SCK cycles as are

necessary. Without a pause, the Q data is transferred next

as shown in Figure 29(a). If the PACKED control bit is

high, then the I and Q components are sent as a double

length word with only one SFS strobe as shown in Figure

29(b). If both channels are multiplexed out the same serial

pin, then the subsequent I/Q channel words will be trans-

mitted immediately following the first I/Q pair as shown

in Figure 29(c). Figure 29(c) also shows how the RDY

signal can be used to identify the I and Q channels in the

TDM serial transmission.The serial output rate is pro-

grammable using the RATE register as a integer division

of the input clock, the division ratio ranging from 1 to 256.

The serial interface will not work properly if the pro-

grammed rate of SCK is insufficient to clock out all the

bits in one OSP.

Serial Port Output Number Formats

Several numeric formats are selectable using the FOR-

MAT control register. The I/Q samples can be rounded to

16 or 24 bits, or truncated to 8 bits. The packed mode

works as described above for these fixed point formats. A

floating point format with 138dB of dynamic range in 12

bits is also provided. The mantissa (m) is 8 bits and the

exponent (e) is 4 bits. The MSB of each segment is trans-

DIVIDE

BOUT

AOUT

RATE

POUT_SEL[2..0]

POUT[15..0]

POUT_EN

SCK

RDY

MUX

RDY_POL, SCK_POL, SFS_POL

Figure 28

CLC5902 output circuit

SFS

SCK

MUX_MODE

SERIAL OUTPUTS

AOUT

BOUT

OUTA

OUTB

OUTA, OUTB

LOW

Table 2

TDM Modes

CLC5902 Datasheet(PDF) 18 Page - National Semiconductor (TI)

CLC5902 Datasheet(HTML) 18 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL