LP3950SLSLASHNOPB datasheet(4/38 Pages) TI1

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LP3950

SNVS331C – NOVEMBER 2004 – REVISED APRIL 2013

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1) (2) (3)

V (SW, FB, R1–2, G1–2, B1–2)

(4) (5)

−0.3V to +7.2V

VDD1, VDD2, VDDIO, VDDA

−0.3V to +6.0V

Voltage on ASE, AD1, AD2

−0.3V to VDD1 +0.3V with 6.0V max

Voltage on Logic Pins

−0.3V to VDD_IO+0.3V with 6.0V max

I (R1, G1, B1, R2, G2, B2)

(6)

150 mA

I (VREF)

10 µA

Continuous Power Dissipation

(7)

Internally Limited

Junction Temperature (TJ-MAX)

125°C

Storage Temperature Range

−65°C to +150°C

Maximum Lead Temperature

260°C

(Reflow soldering, 3 times) (8)

ESD Rating (9)

Human Body Model:

2 kV

Machine Model:

200V

(1)

All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).

(2)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed

performance limits and associated test conditions, see the Electrical Characteristics tables.

(3)

If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4)

Battery/Charger voltage should be above 6.0V no more than 10% of the operational lifetime.

(5)

Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1, VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1,

VDD2 and VDDA are not available (ON) at all conditions, Texas Instruments does not guarantee any parameters or reliability for this

device. Also, VDD1, VDD2 and VDDA must be at the same electric potential.

(6)

The total load current of the boost converter should be limited to 300 mA.

(7)

Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160°C (typ.) and

disengages at TJ = 140°C (typ.).

(8)

For detailed package and soldering specifications and information, please refer to Texas Instruments Application Note 1125 (SNAA002):

Laminate CSP/FBGA.

(9)

The Human body model is a 100 pF capacitor discharged through a 1.5 k

Ω resistor into each pin. The machine model is a 200 pF

capacitor discharged directly into each pin. MIL-STD-883 3015.7

Operating Ratings

(1) (2)

V (SW, FB, R1–2, G1–2, B1–2)

0V to 6.0V

VDD1, VDD2, VDDA

(3)

2.7V to 2.9V

VDDIO

1.65V to VDD1,2 V

Voltage on ASE, AD1, AD2

0.1V to VDD1 - 0.1V

Recommended Load Current

0 mA to 300 mA

Junction Temperature (TJ) Range

−40°C to +125°C

Ambient Temperature (TA) Range

(4)

−40°C to +85°C

(1)

Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed

performance limits and associated test conditions, see the Electrical Characteristics tables.

(2)

All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA).

(3)

Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1, VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1,

VDD2 and VDDA are not available (ON) at all conditions, Texas Instruments does not guarantee any parameters or reliability for this

device. Also, VDD1, VDD2 and VDDA must be at the same electric potential.

(4)

In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =

125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (

θJA), as given by the following equation: TA-MAX = TJ-MAX-OP − (θJA x PD-MAX).

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