LP8501TMXSLASHNOPB datasheet(30/51 Pages) TI1

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LP8501

SNVS548D – SEPTEMBER 2008 – REVISED AUGUST 2013

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Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

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Slave device sends acknowledge signal if the slave address is correct

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition

Auto Increment Feature

The auto increment feature allows writing several consecutive registers within one transmission. Every time an 8-

bit word is sent to the LP8501, the internal address index counter will be incremented by one and the next

feature is enabled by writing the EN_AUTO_INCR bit high in the MISC register (address 36h). Note that the

serial bus address auto increment is not supported for register addresses from 16h to 1Eh (PWM registers).

MASTER

START

CHIP

WRITE

REG

DATA

STOP

ADDR =

ADDR

32H

LP8501

ACK

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LP8501TMX/NOPB Datasheet(PDF) 30 Page - Texas Instruments

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