ductor then developed by the IEEE to enhance the per-

formance of backplane buses BTL compatible transceivers

feature low output capacitance drivers to minimize bus load-

ing a 1V nominal signal swing for reduced power consump-

tion and receivers with precision thresholds for maximum

noise immunity BTL eliminates settling time delays that se-

verely limit TTL bus performance and thus provide signifi-

cantly higher bus transfer rates The backplane bus is in-

tended to be operated with termination resistors (selected

to match the bus impedance) connected to 21V at both

ends The low voltage is typically 1V

Separate ground pins are provided for each BTL output to

minimize induced ground noise during simultaneous switch-

ing

The transceiver’s control and driver inputs are designed

with high impedance PNP input structures and are fully TTL

compatible

The receiver is a high speed comparator that utilizes a

bandgap reference for precision threshold control allowing

maximum noise immunity to the BTL 1V signaling level

the effects of high current switching noise The output is

TRI-STATE

and fully TTL compatible

which this transceiver places on the bus The signal names

on the backplane bus

The DS3885 implements an odd parity check on the arbitra-

signal PER will indicate the parity check result For a quick

indication of current bus conditions the bus status block

generates ALL1 (all asserted) status when all bits

by the DS3875 Arbitration Controller to detect the Arbitra-

tion message number (during phase 1) or the powerfail mes-

sage number (during phase 2)

To latch the arbitration number into the transceiver it is

LE signal is

asserted When the CMPT signal is asserted the arbitration

GT

signal serves two purposes during the arbitration cycle If

the CMPT signal is not asserted during the arbitration cycle

the transceiver compares its internally latched number to

ber on the transceiver is greater than or equal to the number

GT signal is asserted

However if the CMPT signal is asserted the transceiver

participates in the competition If the transceiver wins the

arbitration the WIN

GT signal is asserted to confirm the

winning The AB

RE signal is used to enable the on-chip

receiver outputs

The DS3885 supports live insertion as defined in IEEE

8962 through the LI (Live Insertion) pin To implement live

insertion the LI pin should be connected to the live insertion

power connector If this function is not supported the LI pin

glitch free power-updown protection during power se-

quencing

The DS3885 has two types of power connections in addition

provide the supply voltage for the logic and control circuitry

Multiple power pins reduce the effects of package induc-

tance and thereby minimize switching noise As these pins

difference should never exist between these pins and the

other pins except for BTL IO’s and LI pins requires that any

a

05V

There are three different types of ground pins on the

DS3885 They are the logic ground (GND) BTL grounds

(AB0GND – AB7GNDABPGND) and the Bandgap refer-

ence ground (QGND) All of these reference pins are isolat-

ed within the chip to minimize the effects of high current

switching transients For optimum performance the QGND

should be returned to the connector through a quiet channel

that does not carry transient switching current The GND

and AB0GND – AB7GNDABPGND should be connected to

the nearest backplane ground pin with the shortest possible

path

Since many different grounding schemes could be imple-

mented and ESD circuitry exists on the DS3885 it is impor-

tant to note that any voltage difference between ground

pins QGND GND or AB0GND – AB7GND and ABPGND

quencing

Three additional transceivers are included in the Future-

The DS3884A BTL Handshake Transceiver features select-

able Wired-OR glitch filtering The DS3886A BTL 9-bit

Latching Data Transceiver contains edge triggered latches

in the driver which may be bypassed during a fall-through

mode In addition the device contains a transparent latch in

the receiver section

The DS3875 Arbitration Controller included in the Future-

used in conjunction with the DS3884A and DS3885 trans-

ceivers

signed for IEEE 8961 The LIFE will handle all handshaking

compelled mode data transfer as both master and slave

The Protocol Controller can be configured to operate in

compliance to IEEE 8962 Profile B mode The LIFE incor-

porates a DMA controller and 64-bit FIFO’s for fast queuing

All of the transceivers are offered in 44-pin PLCC and PQFP

high density package styles

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