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TMS570LS0232PZ Datasheet(PDF) 53 Page - Texas Instruments

Part # TMS570LS0232PZ
Description  16- and 32-Bit RISC Flash Microcontroller
PDF  109 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS570LS0232PZ Datasheet(HTML) 53 Page - Texas Instruments

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TMS570LS0232
www.ti.com
SPNS242A – OCTOBER 2014 – REVISED JUNE 2015
The parity protection for peripheral RAMs is not enabled by default and must be enabled by the
application. Each individual peripheral contains control registers to enable the parity protection for
accesses to its RAM.
NOTE
The CPU read access gets the actual data from the peripheral. The application can choose
to generate an interrupt whenever a peripheral RAM parity error is detected.
6.14 On-Chip SRAM Initialization and Testing
6.14.1 On-Chip SRAM Self-Test Using PBIST
6.14.1.1 Features
•
Extensive instruction set to support various memory test algorithms
•
ROM-based algorithms allow the application to run TI production-level memory tests
•
Independent testing of all on-chip SRAM
6.14.1.2 PBIST RAM Groups
Table 6-22. PBIST RAM Grouping
TEST PATTERN (ALGORITHM)
MARCH 13N(1)
MARCH 13N(1)
TRIPLE READ
TRIPLE READ
TWO PORT
SINGLE PORT
MEMORY
RAM GROUP
TEST CLOCK
MEM TYPE
SLOW READ
FAST READ
(CYCLES)
(CYCLES)
ALGO MASK
ALGO MASK
ALGO MASK
ALGO MASK
0x1
0x2
0x4
0x8
PBIST_ROM
1
ROM CLK
ROM
X
X
STC_ROM
2
ROM CLK
ROM
X
X
DCAN1
3
VCLK
Dual Port
12720
DCAN2
4
VCLK
Dual Port
6480
RAM
6
HCLK
Single Port
133160
MIBSPI1
7
VCLK
Dual Port
33440
VIM
10
VCLK
Dual Port
12560
MIBADC
11
VCLK
Dual Port
4200
N2HET1
13
VCLK
Dual Port
25440
HTU1
14
VCLK
Dual Port
6480
(1)
There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the
ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
Copyright © 2014–2015, Texas Instruments Incorporated
System Information and Electrical Specifications
53
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