DS92CK16 datasheet(2/11 Pages) NSC

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Connection Diagram

TSSOP Package Pin Description

Pin Name

Pin #

Type

Description

CLKI/O+

I/O

True (Positive) side of the differential clock input.

CLKI/O−

I/O

Complementary (Negative) side of the differential clock input.

OE; this pin is active Low. When High, this pin forces all CLK

OUT

pins High. When Low, CLK

OUT pins logic state is determined by

either the CrdCLK

IN or the VID at the CLK/I/O pins with respect to

the logic level at the DE pin. This pin has a weak pullup device to

CC. If OE is floating, then all CLKOUT pins will be High.

DE; this pin is active LOW. When Low, this pin enables the

CardCLK

IN signal to the CLKI/O pins and CLKOUT pins. When High,

the Driver is TRI-STATE®, the CLKI/O pins are inputs and determine

the state of the CLK

OUT pins. This pin has a weak pullup device to

CC. If DE is floating, then CLKI/O pins are TRI-STATE.

CLK

OUT

13, 15, 17, 19, 21,

6 Buffered clock (CMOS) outputs.

CrdCLK

Input clock from Card (CMOS level or TTL level).

16, 20, 24

Power

CC; Analog VCCA (Internally separate from VCC, connect externally

or use separate power supplies). No special power sequencing

required. Either V

CCA or VCC can be applied first, or simultaneously

apply both power supplies.

GND

1, 12, 14, 18, 22

Ground

GND

CCA

Power

Analog V

CCA (Internally separate from VCC, connect externally or use

separate power supplies). No special power sequencing required.

Either V

CCA or VCC can be applied first, or simultaneously apply both

power supplies.

GNDA

5, 8

Ground

Analog Ground (Internally separate from Ground must be connected

externally).

3, 10

No Connects

DS101082-2

Order Number DS92CK16TMTC

See NS Package Number MTC24

DS92CK16 Datasheet(PDF) 2 Page - National Semiconductor (TI)

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