MPC9447D datasheet(3/12 Pages) MOTOROLA

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MPC9447

TIMING SOLUTIONS

MOTOROLA

Table 4. Absolute Maximum Ratingsa

Symbol

Characteristics

Min

Max

Unit

Condition

VCC

Supply Voltage

-0.3

3.9

VIN

DC Input Voltage

-0.3

VCC +0.3

VOUT

DC Output Voltage

-0.3

VCC +0.3

IIN

DC Input Current

±20

IOUT

DC Output Current

±50

Storage temperature

-65

125

°C

a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

Table 5. DC Characteristics (VCC =3.3V ± 5%, TA =40°Cto+85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

VIH

Input High Voltage

2.0

VCC +0.3

LVCMOS

VIL

Input Low Voltage

--0.3

0.8

LVCMOS

VOH

Output High Voltage

2.4

IOH =-24 mAa

VOL

Output Low Voltage

0.55

0.30

IOL =24mA

IOL =12mA

ZOUT

Output Impedance

Ω

IIN

Input Currentb

±300

µA

VIN =VCC or GND

ICCQ

Maximum Quiescent Supply Currentc

2.0

All VCC Pins

a. The MPC9447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for

VCC=3.3V).

b. Inputs have pull-down or pull-up resistors affecting the input current.

c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 6. AC Characteristics (VCC =3.3V ± 5%, TA =--40°Cto+85°C)a

Symbol

5Characteristics

Min

Typ

Max

Unit

Condition

fref

Input Frequency

350

MHz

fmax

Output Frequency

350

MHz

fP,REF

Reference Input Pulse Width

1.4

tr,tf

CCLK0, CCLK1 Input Rise/Fall Time

1.0b

0.8to2.0V

tPLH/HL

Propagation Delay

CCLK0 or CCLK1 to any Q

1.3

3.3

tPLZ, HZ

Output Disable Time

tPZL, ZH

Output Enable Time

Setup Time

CCLK0 or CCLK1 to CLK_STOPc

0.0

Hold Time

CCLK0 or CCLK1 to CLK_STOPc

1.0

tsk(O)

Output-to-Output Skew

150

tsk(PP)

Device-to-Device Skew

2.0

tSK(P)

DCQ

Output Pulse Skewd

Output Duty Cycle

fQ<170 MHz

300

DCREF = 50%

tr,tf

Output Rise/Fall Time

0.1

1.0

0.55 to 2.4V

tJIT(CC)

Cycle-to-cycle jitter

RMS (1 σ)

TBD

a. AC characteristics apply for parallel output termination of 50Ω to VTT.

b. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input

pulse width, output duty cycle and maximum frequency specifications.

c. Setup and hold times are referenced to the falling edge of the selected clock signal input.

d. Output pulse skew is the absolute difference of the propagation delay times: | tPLH -tPHL |.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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