DA9155M datasheet(17/36 Pages) DIALOG

17 / 36 page

DA9155M

2.5 A Companion Charger for rapid charging

10.1.2

nIRQ

nIRQ is a level sensitive interrupt signal. It can be configured either as a push-pull or as an open

drain output (IRQ_TYPE), and the polarity can be selected (IRQ_LEVEL). The structure of the

interrupt logic is depicted in Figure 11.

nIRQ is asserted when an un-masked event is asserted. The nIRQ will not be released until all event

registers have been cleared. New events that occur during reading an event register will be held until

the event register has been cleared, ensuring that the host processor does not miss them.

AND

nIRQ

E_RDY

E_TJUNC_WARN

E_VBAT_OV

E_VBAT_UV

E_TIMER

E_VIN_DROP

M_RDY

M_TJUNC_WARN

M_VBAT_OV

M_VBAT_UV

M_TIMER

M_VIN_DROP

AND

E_xx

M_xx

AND

IRQ_LEVEL

IRQ_TYPE

AND

E_EN_BLOCK

M_EN_BLOCK

Figure 11: DA9155M interrupt logic

10.2 2-wire interface

The 2-wire interface provides access to control and status registers. The interface supports

operations compatible to standard, fast, fast-plus and high speed mode of the I

2C bus specification

Rev. 3.

Communication on the 2-wire bus is always between two devices, one acting as the master and the

other as the slave. The DA9155M will only operate as a slave.

SCL carries the 2-wire clock and SDA carries the bi-directional data. The 2-wire interface is open-

drain supporting multiple devices on a single line. The bus lines have to be pulled high by external

pull-up resistors (2 –20

kΩ). These are often shared between multiple devices connected to the

interface. The attached devices only drive the bus lines low by connecting them to ground. As a

result, two devices cannot conflict if they drive the bus simultaneously. In standard/fast mode the

highest frequency of the bus is 400 kHz. The exact frequency can be determined by the application

and it does not have any relation to the DA9155M internal clock signals. DA9155M will follow the

host clock speed within the described limitations and does not initiate any clock arbitration or slow

down. An automatic interface reset can be triggered in case the clock signal ceases to toggle for

>35 ms (controlled in 2W_TO).

Bus clear, if the SDA is stuck, is achieved after receiving 9 clock pulses. Operation in high speed

mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order

to enable spike suppression and slope control characteristics compatible to the I

2C specification. The

high speed mode can be enabled on a transfer-by-transfer basis by sending the master code (0000

1XXX) at the beginning of the transfer. The DA9155M does not make a use of clock stretching and

delivers read data without additional delay up to 3.4 MHz.

Alternatively the interface can be configured to use high speed mode continuously via PM_IF_HSM,

so that the master code is not required at the beginning of every transfer. This reduces

communication overhead on the bus, but limits the attachable bus slaves to compatible devices.

Datasheet

v3.05

22-July-2016

CFR0011-120-00 Rev 5

17 of 36

DA9155M Datasheet(PDF) 17 Page - Dialog Semiconductor

DA9155M Datasheet(HTML) 17 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL