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DA9210

DA9210 Multi-Phase 12 A DC-DC Buck Converter

Datasheet

Revision 2.0

09-Sep-2016

CFR0011-120-00

39 of 90

If GPIO2_PIN = 01 the port will be configured for IPHASE operation as an input or an output,

according to the voltage level on the VOUT_SENSE Pin, see Section 8.3.3. In master mode the port

is an output. In slave mode (VOUT_SENSE must be tied high to VDDCORE) the port is an input.

If GPIO2_PIN = 01 and master mode is configured, whenever the buck converter is enabled, the

signal from the current sense amplifier of one phase is internally routed to the IPHASE pin and is

available externally. This allows the DA9210 to operate as a master together with another slave

instance of DA9210 in dual DA9210 operation.

If GPIO2_PIN = 01 and slave mode is configured, whenever the buck converter is enabled, the signal

applied at the IPHASE pin will be internally routed as a replacement for the current sense amplifier of

one phase, thereby overriding the function of that current sense amplifier in the current regulation

loop. This allows the DA9210 to operate as a slave together with another master instance of DA9210

in dual DA9210 operation.

8.2.6

BUCK_CLK / GPIO3

This port is multi-functional according to the configuration GPIO3_PIN. It can be used as a digital pin

to support the dual parallel mode operation of DA9210 (input in the case of operation as a slave,

output in the case of operation as a master, see Section 8.3.3. Alternatively it behaves like a

standard GPIO extender pin, see Section 8.4.

If GPIO3_PIN = 01 the port will be configured for buck clock operation as an input or an output,

according to the voltage level at VOUT_SENSE pin, see Section 8.3.3. In master mode the port is an

output. In slave mode (VOUT_SENSE must be tied high to VDDCORE) the port is an input.

If GPIO3_PIN = 01 and master mode is configured, whenever the buck converter is enabled, the

clock signal of the buck converter is internally routed to the BUCK_CLK pin and is available

externally. This allows to use DA9210 in dual operation as a master together with another slave

instance of DA9210.

If GPIO3_PIN = 01 and slave mode is configured, whenever the buck converter is enabled, the signal

applied at BUCK_CLK pin will be internally routed to the clock generation block of the buck

converter, thereby overriding the functionality of the internal buck clock. This allows the DA9210 to

operate as a slave together with another master instance of DA9210 in dual DA9210 operation.

8.2.7

Digital External Clock Input / GPIO4

This port is multi-functional according to the configuration of GPIO4_PIN. It can be used as digital

external clock input for the system, if a signal of typically 6 MHz is applied to the pin.

NOTE

The clock must already be running and stable before configuring the port via GPIO4_PIN and before enabling

the buck converter. Missing pulses or signals applied at different frequencies than specified may cause

disruption of the IC.

Alternatively it behaves like a standard GPIO extender pin, see Section 8.4.

8.2.8

OC_PG / nIRQ

The OC_PG (Over Current alarm and Power Good) is an output port shared with nIRQ and can be

either push-pull or open-drain (selected via OC_PG_IRQ_TYPE). The port can be configured as

active high or active low via control OC_PG_IRQ_LEVEL.

If OC_PG_IRQ_CONF = 0 the port is used as IRQ line. It indicates that an interrupt causing event

has occurred and that the event/status information is available in the related registers 0x50 to 0x53.

Such information can be a warning of critical temperature, fault conditions, or status changes on GPI

ports. The event registers hold information about the events that have occurred. Events are triggered

by a status change at the monitored signals. When an event bit is set, the nIRQ signal is asserted

(unless this interrupt is masked by a corresponding bit in the IRQ mask registers 0x54 and 0x55).

The nIRQ is not released until all event registers with asserted bits have been read and cleared. New

DA9210 Datasheet(PDF) 39 Page - Dialog Semiconductor

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