ICS8624 datasheet(1/16 Pages) ICST

Part #	ICS8624

Description	LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

PDF	16 Pages

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Manufacturer	ICST [Integrated Circuit Systems]

Direct Link	http://www.icst.com

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1 / 16 page

8624BY

www.icst.com/products/hiperclocks.html

REV. C JUNE 15, 2004

1

Integrated

Circuit

Systems, Inc.

ICS8624

LOW SKEW, 1-TO-5

DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

GENERAL DESCRIPTION

The ICS8624 is a high performance, 1-to-5

Differential-to-HSTL zero delay buffer and

a member of the HiPerClockS™ family of High

Performance Clock Solutions from ICS. The

ICS8624 has two selectable clock input pairs.

The CLK0, nCLK0 and CLK1, nCLK1 pair can accept most

standard differential input levels. The VCO operates at a fre-

quency range of 250MHz to 700MHz. Utilizing one of the

outputs as feedback to the PLL, output frequencies up to

700MHz can be regenerated with zero delay with respect to

the input. Dual reference clock inputs support redundant clock

or multiple reference applications.

BLOCK DIAGRAM

PIN ASSIGNMENT

FEATURES

• Fully integrated PLL

• 5 differential HSTL outputs

• Selectable differential CLKx, nCLKx input pairs

• CLKx, nCLKx pairs can accept the following differential

input levels: LVPECL, LVDS, HSTL, SSTL, HCSL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

• Cycle-to-cycle jitter: 25ps (maximum)

• Output skew: 25ps (maximum)

• Static phase offset: ±100ps

• 3.3V core, 1.8V output operating supply

• 0°C to 70°C ambient operating temperature

• Lead-Free package available

• Industrial temperature information available upon request

32 31 30 29 28 27 26 25

9

10 11 12 13 14 15 16

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

VDDO

Q3

nQ3

Q2

nQ2

Q1

nQ1

VDDO

SEL0

SEL1

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

MR

32-Lead LQFP

7mm x 7mm x 1.4mm body package

Y Package

Top View

ICS8624

HiPerClockS™

ICS

PLL_SEL

CLK0

nCLK0

CLK1

nCLK1

CLK_SEL

FB_IN

nFB_IN

SEL0

SEL1

MR

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

Q4

nQ4

0

1

PLL

0

1

÷4, ÷8

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