MIC45404 datasheet(17/32 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005478A-page 17

MIC45404

4.12

Overcurrent Protection (ILIM) and

Hiccup Mode Short-Circuit

Protection

The MIC45404 features instantaneous cycle-by-cycle

current limit with current sensing, both on the low-side

and high-side switches. It also offers a Hiccup mode for

prolonged overloads or short-circuit conditions.

The low-side cycle-by-cycle protection detects the cur-

rent level of the inductor current during the low-side

MOSFET on time. The high-side MOSFET turn-on is

inhibited as long as the low-side MOSFET current limit is

above the overcurrent threshold level. The inductor cur-

rent will continue decaying until the current falls below

the threshold, where the high-side MOSFET will be

enabled again, according to the duty cycle requirement

from the PWM modulator.

The low-side current limit has three different program-

mable levels (for 3A, 4A and 5A loads) in order to fit

different application requirements. Since the low-side

current limit acts on the valley current, the DC output

current level (IOUT), where the low-side cycle-by-cycle

current limit is engaged, will be higher than the current

limit value by an amount equal to

ILPP/2, where ILPP

is the peak-to-peak inductor ripple current.

The

high-side

current

limit

approximately

1.4-1.5 times greater than the low-side current limit

(typical values). The high-side cycle-by-cycle current

limit immediately truncates the high-side on time

without waiting for the off clocking event.

A Leading-Edge Blanking (LEB) timer (108 ns, typical)

is provided on the high-side cycle-by-cycle current limit

to mask the switching noise and to prevent falsely

triggering the protection. The high-side cycle-by-cycle

current limit action cannot take place before the LEB

timer expires.

Hiccup mode protection reduces power dissipation in

permanent short-circuit conditions. On each clock

cycle, where a low-side cycle-by-cycle current limit

event is detected, a 4-bit up/down counter is incre-

mented. On each clock cycle without a concurrent

low-side current limit event, the counter is decremented

or left at zero. The counter cannot wraparound below

‘0000’ and above ‘1111’. High-side current limit events

do not increment the counter. Only detections from

low-side current limit events trigger the counter.

If the counter reaches ‘1111’ (or 15 events), the high

and low-side MOSFETs become tri-stated, and power

delivery to the output is inhibited for the duration of

three times the soft start time. This digital integration

mechanism provides immunity to momentary overload-

ing of the output. After the wait time, the MIC45404

retries entering operation and initiates a new soft start

sequence.

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