DM9301

100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter

18

Preliminary

Version: DM9301-DS-F02

May 8, 2000

5-Bit Symbol 100Base-TX/FX Transmit Timing Parameters

Symbol

Parameter

Min.

Typ.1

Max.

Unit

Conditions

s

TXD[4:0] Setup To TX_CLK High

11

-

-

ns

h

TXD[4:0] Hold From TX_CLK

High

0-

-

ns

pdtpo

TXD[4:0] Sampled To TPTXO

(TXD to TP Latency)

--

6

BT

pdfxo

TXD[4:0] Sampled To PECLTXO

(TXD to FX Latency)

--

4

BT

r/f

100TX Driver Rise/Fall Time

3

4

5

ns

90% To 10%, Into

100ohm Differential

1. Typical values are at 25and are for design aid only; not guaranteed and not subject to production testing.

5-Bit Symbol 100Base-TX/FX Receive Timing Diagram

RXCLK

RXD [4:0]

TX RXI+/-

S

h

FX RXI+/-

pdtxi

pdfxi

5-Bit Symbol 100Base-TX/FX Receive Timing Parameter

Symbol

Parameter

Min.

Typ1.

Max.

Unit

Conditions

s

RXD[4:0) Setup To RX_CLK

High

10

-

-

ns

h

RXD[4:0]Hold From RX_CLK

High

10

-

-

ns

pdtxi

TXRXI In To RXD[0:3] Out (Rx

Latency)

--

6

BT

pdfxi

PECLRDI In To RXD[4:0] Out

(Rx Latency)

--

4

BT