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ML7344C Datasheet(PDF) 21 Page - LAPIS Semiconductor Co., Ltd. |
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ML7344C Datasheet(HTML) 21 Page - LAPIS Semiconductor Co., Ltd. |
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21 / 154 page ![]() FEDL7344C/E/J-05 ML7344C/E/J 21/154 ●DIO interface characteristics Item Symbol Condition Min Typ. Max Unit DIO Input setup time TDISU 1 - - µs DIO Input hold time TDIH 0 - - ns DIO Output hold time TDOH 20 - - ns DCLK frequency accuracy in TX (*1) FDCLK_TX (*3) - (*3) kHz DCLK frequency accuracy in RX (*2) FDCLK_RX -30 - +30 % DCLK output duty ratio (TX) DDCLK_TX 45 - 55 % DCLK output duty ratio (RX) DDCLK_RX Load capacitance CL=20pF 30 - 70 % (*1) DCLK clock frequency in TX mode will be varied depending on the variance of master clock frequency. (*2) DCLK clock frequency in RX mode will be varied by reproduced clock and its jitter. (*3) These values are equal to the accuracy of the master clock frequency NOTE: All timing parameter is defined at voltage level of VDDIO * 20% and VDDIO * 80%. DCLK DIO(input) VALID VALID VALID FDCLK_TX/ FDCLK_RX TDISU TDIH DIO(output) VALID VALID VALID TDOH |
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