VITESSE

SEMICONDUCTOR CORPORATION

Target Specification

VSC8115

STS-12/STS-3 Multi Rate

Clock and Data Recovery Unit

Page 10

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/29/00

G52272-0, Rev. 1.1

Table 10: Pin Identification

Signal

I/O

Level

Pin Description

DATAIN+/-

I

LVPECL

Receive data in. The high speed output clock (CLKOUT+/-) is

recovered from this high speed differential input data.

DATAOUT+/-

O

LVDS/LVPECL

High speed differential data out. This is the retimed version of the

receive data input (DATAIN+/-). Can be configured as either LVDS

or LVPECL signal.

CLKOUT+/-

O

LVDS/LVPECL

High speed differential clock out This clock is recovered from the

receive data input (DATAIN+/-). Can be configured as either LVDS

or LVPECL signal.

STS12

I

LVTTL

STS-12 or STS-3 mode selection. Set HIGH to select the STS-12

operation. Set LOW to select the STS-3 operation.

LOCKREFN

I

LVTTL

Lock to REFCLK input. When set LOW, it holds the CLKOUT+/-

output to within +500ppm of the REFCLK input, and it forces the

DATAOUT+/- output to the LOW state.

SD

I

LVPECL

Signal Detect. SD should be connected to the SD output on the

optical module. SD is active HIGH. When SD is set HIGH, it means

that there is sufficient optical power. When SD is set LOW to

indicate loss of signal condition, the CLKOUT+/- output signal will

be held to within +500ppm of the REFCLK input; in additions, the

DATAOUT+/- will be held in the LOW state.

REFCLK

I

LVTTL

19.44 MHz local reference clock input for the CRU. REFCLK is used

for the PLL phase adjustment during power up, and it also serves as a

stable clock source in the absence of serial input data.

LOCKDET

O

LVPECL

Active HIGH to indicate that PLL is locked to serial data input, and

valid clock and data are present at the serial outputs (DATAOUT+/-

and CLKOUT+/-). The LOCKDET will go inactive under the

following conditions:

(1). If SD is set LOW.

(2). If LOCKREFN is set LOW.

(3). If the VCO has drifted away from the local reference

clock REFCLK by more than 500 ppm.

BYPASS

I

LVTTL

Used for production test. Set to VSS for normal operation.

CAP+/CAP-

I

Analog

External loop filter pins. The loop filter capacitor should be

connected to these pins. The capacitor value should be 1.0uF +10%

tolerance.

VDD

+3.3V

+3.3V Power Supply for low speed I/O’s and on-chip digital CMOS

blocks.

VSS

GND

Ground pin for low speed I/O’s and on-chip digital CMOS blocks

VDDA

+3.3V

+3.3V Power Supply for high speed I/O’s and on-chip PLL blocks.

VSSA

GND

Ground pins for high speed I/O’s and on-chip PLL blocks.