BT8960 datasheet(21/104 Pages) ETC

21 / 104 page

1.0 System Overview

1.3 Pin Descriptions

Bt8960

Single-Chip 2B1Q Transceiver

N8960DSB

Channel Unit Interface

RQ[1]/

RDAT

RQ[0]/ BCLK

Receive Quat 1/

Receive Data

Receive Quat 0/

Bit Clock

RQ[1]/RDAT and RQ[0]/BCLK are bimodal outputs that represent the sign and

magnitude bits of the received quaternary output symbol in parallel channel unit

modes (RQ[1], RQ[0]), and the serial-data and bit-clock outputs in serial chan-

nel unit modes (RDAT, BCLK). Behavior of these outputs is conﬁgurable through

the Channel Unit Interface Modes Register [CU_interface_modes; 0x06] for par-

allel master, parallel slave, serial magnitude-bit-ﬁrst and serial sign-bit-ﬁrst

operations.

For parallel mode operation:

RQ[1] = Sign bit output

RQ[0] = Magnitude bit output

Both outputs are updated at the symbol rate on the rising edge of QCLK

(master mode) or the rising/falling edge (programmable) of RBCLK (slave

mode).

For serial mode operation:

RDAT = Serial quaternary data output

BCLK = Bit-rate (two times symbol rate) clock output

RDAT is updated at the bit rate on the rising edge of BCLK

TQ[1]/ TDAT

TQ[0]

Transmit Quat 1/

Transmit Data

Transmit Quat 0

TQ[1]/TDAT and TQ[0] are bimodal inputs that represent the sign and magnitude

bits of the quaternary input symbol to be transmitted in parallel channel unit

modes (TQ[1], TQ[0]), and the serial data input in serial channel unit modes

(TDAT). Interpretation of these inputs is conﬁgurable through the Channel Unit

Interface Modes Register [CU_Interface_modes; 0x06] for parallel master, par-

allel slave, serial magnitude-bit-ﬁrst and serial sign-bit-ﬁrst operations.

For parallel mode operation:

TQ[1] = Sign bit input

TQ[0] = Magnitude bit input

Both inputs are sampled at the symbol rate on the falling edge of QCLK (mas-

ter mode) or the rising/falling edge (programmable) of TBCLK (slave mode).

For serial mode operation:

TDAT = Serial quaternary data input

TQ0 = Don’t care (tie or pull up to supply rail)

TDAT is sampled at the bit rate (two times the symbol rate) on the falling

edge of BCLK.

QCLK

Quaternary Clock

Runs at the symbol rate. It deﬁnes the data on the TQ and RQ interfaces. QCLK

is also used to frame transmit/receive quats in serial mode.

TBCLK

Transmit Baud-

Rate Clock

Functions as the transmit baud-rate clock input. It must be frequency locked to

QCLK. This input is used only when the channel unit interface is in parallel slave

mode. If it is unused, it should be tied to VDD2 or DGND.

RBCLK

Receive Baud-

Rate Clock

Functions as the receive baud-rate clock input. It must be frequency locked to

QCLK. This input is used only when the channel unit interface is in parallel slave

mode. If it is unused, it should be tied to VDD2 or DGND.

Table 1-2. Hardware Signal Deﬁnitions (2 of 4)

Pin Label

Signal Name

I/O

Definition

BT8960 Datasheet(PDF) 21 Page - List of Unclassifed Manufacturers

BT8960 Datasheet(HTML) 21 Page - List of Unclassifed Manufacturers

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL