PC87310 datasheet(17/52 Pages) NSC

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40 Functional Description (Continued)

TABLE 4-5 DUART Reset Configuration

RegisterSignal

Reset Control

Reset State

Interrupt Enable Register

Master Reset

0000

(Note 1)

Interrupt Identification Register

Master Reset

0000

0001

Test Control

Master Reset

0000

Line Control Register

Master Reset

0000

MODEM Control Register

Master Reset

0000

Line Status Register

Master Reset

0110

0000

MODEM Status Register

Master Reset

XXXX

0000

(Note 2)

SOUT

Master Reset

High

INTR (RCVR Errs)

Read LSRMR

LowTRI-STATE

INTR (RCVR Data Ready)

Read RBRMR

LowTRI-STATE

INTR (THRE)

Read IIRWrite THRMR

LowTRI-STATE

INTR (Modem Status Changes)

Read MSRMR

LowTRI-STATE

OUT 2 Bit

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

Note 1

Boldface bits are permanently low

Note 2

Bits 7–4 are driven by the input signals

PROGRAMMABLE BAUD GENERATOR

The DUART contains two independently programmable

Baud Generators The 24 MHz crystal oscillator frequency

input is divided by 13

resulting in a frequency of

18462 MHz This is sent to each Baud Generator and divid-

ed by the divisor for the associated UART The output fre-

quency of the Baud Generator is 16 c the baud rate

divi-

sor

(frequency input) d (baud rate c 16) The output

of each Baud Generator drives the transmitter and receiver

sections of the associated serial channel Two 8-bit latches

per channel store the divisor in a 16-bit binary format These

Divisor Latches must be loaded during initialization to en-

sure proper operation of the Baud Generator Upon loading

either of the Divisor Latches a 16-bit Baud Counter is load-

Table 4-6 provides decimal divisors to use with crystal fre-

quencies of 24 MHz The oscillator input to the chip should

always be 24 MHz to ensure that the Floppy Disk Controller

timing is accurate and that the UART divisors are compati-

ble with existing software Using a divisor of zero is not

recommended

LINE STATUS REGISTER

This 8-bit register provides status information to the CPU

concerning the data transfer Table 4-4 shows the contents

of the Line Status Register Details on each bit follow

Bit 0

This bit is the receiver Data Ready (DR) indicator Bit

0 is set to a logic 1 whenever a complete incoming charac-

ter has been received and transferred into the Receiver

Buffer Register Bit 0 is reset to a logic 0 by reading the data

in the Receiver Buffer Register

TABLE 4-6 Divisors Baud Rates

and Clock Frequencies

Baud Rate

Divisor

18462 MHz Clock

Decimal Divisor

Percent Error

for 16 c Clock

(Note 1)

2304

1536

110

1047

1345

857

150

768

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

Note 1

The percent error for all Baud Rates except where indicated other-

wise is 02%

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