TSB81BA3, TSB81BA3I

IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS559B − DECEMBER 2002 − REVISED OCTOBER 2003

38

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION (1394a−2000 INTERFACE)

transmit (continued)

The sequence of events for a cancelled/null packet transmission is as follows:

(a) Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the

interface to the link.

(b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold. This idle cycle

is optional; the link is not required to assert idle preceding hold.

(c) Optional hold cycles. The link may assert hold for up to 47 cycles preceding assertion of idle. These hold

cycle(s) are optional; the link is not required to assert hold preceding idle.

(d) Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle

on the CTL lines and then releasing the interface and returning control to the PHY. Note that the link may

assert idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert

hold. It is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold

cycles are asserted. This ensures that either the link or PHY controls the interface in all cycles.

(e) After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status

transfer, receive operation, or transmit operation.

interface reset and disable

The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface may be placed into a

reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface

is not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding

bus request or register read request, and ignores any requests made via the LREQ line. Additionally, any status

information generated by the PHY is not queued and does not cause a status transfer upon restoration of the

interface to normal operation.

The LPS signal may be either a level signal or a pulsed signal, depending upon whether the PHY-LLC interface

is a direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY

and LLC the LPS signal must be pulsed. In a direct connection, the LPS signal may be either a pulsed or a level

signal. Timing parameters for the LPS signal are given in Table 21.

Table 21. LPS Timing Parameters

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

TLPSL

LPS low time (when pulsed) (see Note 5)

0.09

2.60

µs

TLPSH

LPS high time (when pulsed) (see Note 5)

0.021

2.60

µs

TLPSH

LPS duty cycle (when pulsed) (see Note 6)

20%

60%

TLPS_RESET

Time for PHY to recognize LPS deasserted and reset the interface

2.60

2.68

µs

TLPS_DISABLE

Time for PHY to recognize LPS deasserted and disable the interface

26.03

26.11

µs

TRESTORE

Time to permit optional isolation circuits to restore during an interface reset

15

23†

µs

TCLK_ACTIVATE Time for PCLK to be activated from reassertion of LPS

PHY not in low-state

60

ns

TCLK_ACTIVATE Time for PCLK to be activated from reassertion of LPS

PHY in low-power state

5.3

7.3

ms

† The maximum value for TRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time may elapse before

LPS is reasserted. Otherwise, in order to reset but not disable the interface it is necessary that the LLC ensure that LPS is deasserted for less

than TLPS_DISABLE.

NOTES:

3. The specified TLPSL and TLPSH times are worst-case values appropriate for operation with the TSB81BA3. These values are broader

than those specified for the same parameters in the 1394a−2000 Supplement (that is, an implementation of LPS that meets the

requirements of 1394a−2000 operates correctly with the TSB81BA3).

4. A pulsed LPS signal must have a duty cycle (ratio of TLPSH to cycle period) in the specified range to ensure proper operation when

using an isolation barrier on the LPS signal (for example, as shown in Figure 8).