PM6344 datasheet(51/256 Pages) PMC

51 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

counter reaches 0. This algorithm biases OOF occurrences, leading to

declaration of red alarm when intermittent loss of frame alignment occurs.

8.4

Performance Monitor Counters (PMON)

The Performance Monitor Counters function is provided by the Performance

Monitor (PMON) block that accumulates CRC error events, frame

synchronization bit error events, line code violation events, and far end block

error events with saturating counters over consecutive intervals as defined by the

period of the supplied transfer clock signal (typically 1 second). When the transfer

clock signal is applied, the PMON block transfers the counter values into holding

registers and resets the counters to begin accumulating events for the interval.

The counters are reset in such a manner that error events occurring during the

reset are not missed. If enabled, an interrupt is generated whenever counter data

is transferred into the holding registers. If the holding registers are not read

between successive transfer clocks, an OVERRUN register bit is asserted.

Generation of the transfer clock within the EQUAD chip is performed by writing to

any counter register location (X4AH to X4FH) or by writing to the EQUAD

Revision/Chip ID/Global PMON Update register (00CH). The holding register

addresses are contiguous to facilitate polling operations.

8.5

HDLC Receiver (RFDL)

The HDLC Receiver function is provided by the RFDL block. The RFDL is a

microprocessor peripheral used to receive LAPD/HDLC frames on either Time

Slot 16 or the National Use bits of Time Slot 0.

The RFDL detects the change from flag characters to the first byte of data,

removes stuffed zeros on the incoming data stream, receives frame data, and

calculates the CRC Q.921 frame check sequence (FCS).

Received data is placed into a 4-level FIFO buffer. The Status Register contains

bits which indicate overrun, end of message, flag detected, and buffered data

available.

On end of message, the Status Register also indicates the FCS status and the

number of valid bits in the final data byte. Interrupts are generated when one,

two or three bytes (programmable via the RFDL configuration register) are stored

in the FIFO buffer. Interrupts are also generated when the terminating flag

sequence, abort sequence, or FIFO buffer overrun are detected.

PM6344 Datasheet(PDF) 51 Page - PMC-Sierra, Inc