5-78

Description of Operation

Initialization and Controls

A positive pulse on the MASTER RESET (MR) input resets

the control, status, and receiver buffer registers, and sets the

serial output (TRO) High. Timing is generated from the clock

inputs RRC and TRC at a frequency equal to 16 times the

serial data bit rate. The RRC and TRC inputs may be driven

by a common clock, or may be driven independently by two

different clocks. The CONTROL REGISTER LOAD (CRL)

input is strobed to load control bits for PARITY INHIBIT (PI),

EVEN PARITY ENABLE (EPE), STOP BIT SELECTS (SBS),

and CHARACTER LENGTH SELECTS (CLS1 and CLS2).

for receiver and/or transmitter operations.

Transmitter Operation

The transmitter section accepts parallel data, formats it, and

transmits it in serial form (Figure 2) on the TRO terminal.

Transmitter timing is shown in Figure 3. (A) Data is loaded

into the transmitter buffer register from the inputs TBR1

through TBR8 by a logic low on the TBRL input. Valid data

rising edge of TBRL. If words less than 8-bits are used, only

the least significant bits are used. The character is right justi-

fied into the least significant bit, TBR1. (B) The rising edge of

TBRL clears TBRE. 1/2 to 11/2 cycles later, depending on

when the TBRL pulse occurs with respect to TRC, data is

transferred to the transmitter register and TRE is cleared.

TBRE is set to a logic High one cycle after that.

Output data is clocked by TRC. The clock rate is 16 times

the data rate. (C) A second pulse on TBRL loads data into

the transmitter buffer register. Data transfer to the transmitter

register is delayed until transmission of the current character

is complete. (D) Data is automatically transferred to the

transmitter register and transmission of that character

begins.

Receiver Operation

Data is received in serial form at the RRl input. When no

data is being received, RRI input must remain high. The data

is clocked through the RRC. The clock rate is 16 times the

data rate. Receiver timing is shown in Figure 4.

(A) A low level on DRR clears the DR line. (B) During the first

stop bit data is transferred from the receiver register to the

RB Register. If the word is less than 8 bits, the unused most

significant bits will be a logic low. The output character is

right justified to the least significant bit RBR1. A logic high on

OE indicates overruns. An overrun occurs when DR has not

been cleared before the present character was transferred to

the RBR. (C) 1/2 clock cycle later DR is set to a logic high

and FE is evaluated. A logic high on FE indicates an invalid

stop bit was received. A logic high on PE indicates a parity

error.

Start Bit Detection

The receiver uses a 16X clock for timing (Figure 5). The start

bit could have occurred as much as one clock cycle before it

was detected, as indicated by the shaded portion. The cen-

ter of the start bit is defined as clock count 7 1/2. If the

receiver clock is a symmetrical square wave, the center of

the start bit will be located within

±1/2 clock cycle ±1/32 bit or

±3.125%. The receiver begins searching for the next start bit

at 9 clocks into the first stop bit.

FIGURE 2. SERIAL DATA FORMAT

5 - 8 DATA BITS

1, 1-1/2 OR

2 STOP BITS

START

BIT

LSB

†

MSB

PARITY

FIGURE 3. TRANSMITTER TIMING WAVEFORMS

END OF

LAST

STOP BIT

1/2 TO 1-1/2 CYCLES

A

1 TO 2 CYCLES

1-1/2 TO 2-1/2 CYCLES

1/2

CLOCK

BC

D

TBRL

TBRE

TRE

TRO

DATA

FIGURE 4. RECEIVER TIMING WAVEFORMS

AB

C

FE, PE

BEGINNING OF FIRST STOP BIT

8 1/2 TO 9 1/2

CLOCK CYCLES

DR

DRR

RBRI-8, OE

RRI

1/2 CLOCK

CYCLES

FIGURE 5. START BIT TIMING WAVEFORMS

ASTART

7 1/2 CLOCK

CYCLES

8 1/2 CLOCK

CYCLES

RRI

INPUT

CLOCK

COUNT 7 1/2

DEFINED CENTER

OF START BIT

CDP6402, CDP6402C