BLUENRG-MSCSP datasheet(15/42 Pages) STMICROELECTRONICS

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BlueNRG-MS

Block diagram and descriptions

A block diagram of the device is shown in Figure 9: "Block diagram". In the following

subsections a short description of each module is given.

Figure 9: Block diagram

5.1

Core, memory and peripherals

The BlueNRG-MS contains an ARM Cortex-M0 microcontroller core that supports ultra-low

leakage state retention mode and almost instantaneously returning to fully active mode on

critical events.

The memory subsystem consists of 64 KB Flash, and 12 KB RAM, divided in two blocks of

6 KB (RAM1 and RAM2). Flash is used for the M0 program. No RAM or FLASH resources

are available to the external microcontroller driving the BlueNRG-MS.

The application controller interface (ACI) uses a standard SPI slave interface as transport

layer, basing in five physical wires:

•

2 control wires (clock and slave select)

•

2 data wires with serial shift-out (MOSI and MISO) in full duplex

•

1 wire to indicate data availability from the slave

Table 4: SPI interface

Name

Direction

Width

Description

SPI_CS

SPI slave select = SPI enable.

SPI_CLK

SPI clock (max 8 MHz).

SPI_MOSI

Master output, slave input.

SPI_MISO

Out

Master input, slave output.

DocID027103 Rev 6

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BLUENRG-MSCSP Datasheet(PDF) 15 Page - STMicroelectronics